iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model
4本节页面
RTL→GDS开源流程
AI可导出状态
GPL-3.0开源许可
本节地图
选择进入本模块的路径
每张卡片对应一份可继续阅读的开放文档。
RTL → GDSII
统一数据库贯穿全流程
01
iMap
Logic synthesis
02
iFP
Floorplanning
03
iPDN
Power delivery
04
iPL
Placement
05
iCTS
Clock tree
06
iTO
Optimization
07
iRT
Routing
08
iDRC
Rule checks