workspace summary - gcd - sky130

Technology information

foundry configs

configs	paths
tech lef	/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_fd_sc_hs.tlef
lefs	['/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_fd_sc_hs_merged.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__com_bus_slice_10um.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__com_bus_slice_1um.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__com_bus_slice_20um.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__com_bus_slice_5um.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__corner_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__disconnect_vccd_slice_5um.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__disconnect_vdda_slice_5um.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__gpiov2_pad_wrapped.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vccd_hvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vccd_lvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vdda_hvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vdda_lvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vddio_hvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vddio_lvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vssa_hvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vssa_lvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vssd_hvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vssd_lvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vssio_hvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_ef_io__vssio_lvc_pad.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_fd_io__top_xres4v2.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130io_fill.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_sram_1rw1r_128x256_8.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_sram_1rw1r_44x64_8.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_sram_1rw1r_64x256_8.lef', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lef/sky130_sram_1rw1r_80x64_8.lef']
libs	['/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lib/sky130_fd_sc_hs__tt_025C_1v80.lib', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lib/sky130_dummy_io.lib', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lib/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lib/sky130_sram_1rw1r_44x64_8_TT_1p8V_25C.lib', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lib/sky130_sram_1rw1r_64x256_8_TT_1p8V_25C.lib', '/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/lib/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib']
sdc	/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/sdc/gcd.sdc
spef	/home/huangzengrong/aieda_0.1/aieda_fork/aieda/third_party/iEDA/scripts/foundry/sky130/spef/gcd.spef

flows

basic information


dbu	1000	die area	16595.365329	core area	16278.105599999999	layer num	13	routing layer	6	cut layer	5	io pin num	56

flow status

step	eda tool	state
floorplan	iEDA	unstart
PDN	iEDA	unstart
fixFanout	iEDA	unstart
place	iEDA	unstart
CTS	iEDA	unstart
optDrv	iEDA	unstart
optHold	iEDA	unstart
legalization	iEDA	unstart
route	iEDA	unstart
drc	iEDA	unstart
vectorization	iEDA	unstart
filler	iEDA	unstart

floorplan

PDN

fixFanout


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iNO - FixFanout	flow_runtime	6.737492 s
flow_memory	3901.028000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	1445	num_nets	675	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.3999911844730377	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.4077869951725006
core_bounding_width	128.64	core_bounding_height	126.54	clock_timings_clock_name	core_clock	clock_timings_origin_clock_name	None	clock_timings_origin_setup_tns	-9.853673999999991
clock_timings_origin_setup_wns	-0.361389	clock_timings_origin_hold_tns	0.0	clock_timings_origin_hold_wns	0.399995	clock_timings_origin_suggest_freq	423.4795707102896	clock_timings_opt_clock_name	None
clock_timings_opt_setup_tns	-9.853673999999991	clock_timings_opt_setup_wns	-0.361389	clock_timings_opt_hold_tns	0.0	clock_timings_opt_hold_wns	0.399995	clock_timings_opt_suggest_freq	423.4795707102896
clock_timings_delta_clock_name	None	clock_timings_delta_setup_tns	0.0	clock_timings_delta_setup_wns	0.0	clock_timings_delta_hold_tns	0.0	clock_timings_delta_hold_wns	0.0
clock_timings_delta_suggest_freq	0.0

place


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iPL - Placement	flow_runtime	14.375453 s
flow_memory	533.944000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	1445	num_nets	675	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.3999911844730377	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.4077869951725006
core_bounding_width	128.64	core_bounding_height	126.54	bin_number	16384	bin_size_x	2010	bin_size_y	1978
fix_inst_cnt	806	instance_cnt	1445	net_cnt	675	overflow_number	1689	overflow	0.24913085997104645
total_pins	1780	dplace_place_density	0.0	dplace_HPWL	11633252	dplace_STWL	12718247	gplace_place_density	0.4433000385761261
gplace_HPWL	11548128	gplace_STWL	12631717	lg_summary	None

CTS


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iPL - Placement	flow_runtime	18.152465 s
flow_memory	0.000000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	1449	num_nets	679	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.40149763226509094	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.4093228280544281
core_bounding_width	128.64	core_bounding_height	126.54	buffer_num	4	buffer_area	25.5744	clock_path_min_buffer	2
clock_path_max_buffer	2	max_level_of_clock_tree	2	max_clock_wirelength	225	total_clock_wirelength	834.8129999999999	clocks_timing_clock_name	core_clock
clocks_timing_setup_tns	-10.976467999999997	clocks_timing_setup_wns	-0.455913	clocks_timing_hold_tns	0.0	clocks_timing_hold_wns	0.43328	clocks_timing_suggest_freq	407.1805475193951
static_power	None	dynamic_power	None

optDrv


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iTO - Fix DRV	flow_runtime	18.731059 s
flow_memory	3901.108000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	1449	num_nets	679	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.40149763226509094	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.4093228280544281
core_bounding_width	128.64	core_bounding_height	126.54	HPWL	4.66180346600637e-310	STWL	6.93969820014917e-310	clock_timings_clock_name	core_clock
clock_timings_origin_tns	-54.75283899999997	clock_timings_origin_wns	-1.195516	clock_timings_origin_suggest_freq	312.9385050802437	clock_timings_opt_tns	-54.75283899999997	clock_timings_opt_wns	-1.195516
clock_timings_opt_suggest_freq	312.9385050802437	clock_timings_delta_tns	0.0	clock_timings_delta_wns	0.0	clock_timings_delta_suggest_freq	0.0

optHold


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iTO - Fix Hold	flow_runtime	18.162733 s
flow_memory	3942.812000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	1449	num_nets	679	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.40149763226509094	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.4093228280544281
core_bounding_width	128.64	core_bounding_height	126.54	HPWL	4.66180346600637e-310	STWL	6.93969820014917e-310	clock_timings_clock_name	core_clock
clock_timings_origin_tns	-54.75283899999997	clock_timings_origin_wns	-1.195516	clock_timings_origin_suggest_freq	312.9385050802437	clock_timings_opt_tns	-54.75283899999997	clock_timings_opt_wns	-1.195516
clock_timings_opt_suggest_freq	312.9385050802437	clock_timings_delta_tns	0.0	clock_timings_delta_wns	0.0	clock_timings_delta_suggest_freq	0.0

legalization


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iPL - Placement	flow_runtime	7.290393 s
flow_memory	533.944000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	1449	num_nets	679	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.40149763226509094	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.4093228280544281
core_bounding_width	128.64	core_bounding_height	126.54	pl_common_summary_place_density	None	pl_common_summary_HPWL	12016945	pl_common_summary_STWL	12964018
lg_total_movement	0	lg_max_movement	0

route


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iRT - Routing	flow_runtime	0.000000 s
flow_memory	0.000000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	1449	num_nets	679	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.40149763226509094	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.4093228280544281
core_bounding_width	128.64	core_bounding_height	126.54

drc

	met1	met2	met3	met4	met5	total
cut_short	0	0	0	2	0	2
metal_short	0	0	0	22	6	28
minimum_width	0	0	0	0	3	3
nonsufficient_metal_overlap	0	0	0	0	1	1
out_of_die	0	0	0	2	2	4
parallel_run_length_spacing	18	6	7	12	1	44
same_layer_cut_spacing	0	0	0	6	0	6
total	18	6	7	44	13	88

filler


eda_tool	iEDA	eda_version	V23.03-OS-01	design_version	5.8	flow_stage	iPL - Filler	flow_runtime	3.512568 s
flow_memory	0.000000 MB	num_layers	13	num_layers_routing	6	num_layers_cut	5	num_iopins	56
num_instances	2916	num_nets	679	num_pdn	2	design_dbu	1000	die_area	16595.365329
die_usage	0.9032039642333984	die_bounding_width	128.823	die_bounding_height	128.823	core_area	16278.105599999999	core_usage	0.920807421207428
core_bounding_width	128.64	core_bounding_height	126.54

Design analysis

Design features

design statis

Result Statistics Analysis Report

Total designs analyzed: 1
Accessible designs: 0/1 (0.0%)

File Statistics Summary

Nets: 0 files, 0 B
Patches: 0 files, 0 B
Paths: 0 files, 0 B

Top 3 Designs by Total File Count

GCD: 0 files, 0 B

cell type

Cell Type Distribution Analysis Report

Analyzed 1 design(s) with 681 total instances

Instance Type Statistics

Clock: 38 (5.6%) - Min: 38, Max: 38, Avg: 38.0
Logic: 643 (94.4%) - Min: 643, Max: 643, Avg: 643.0
Macros: 0 (0.0%) - Min: 0, Max: 0, Avg: 0.0
Iopads: 0 (0.0%) - Min: 0, Max: 0, Avg: 0.0

Top 3 Designs by Total Instance Count

1. GCD: 681 instances

core usage

Core Usage Analysis Report

Analyzed 1 design(s)
Average core usage: 40.93%
Usage range: 40.93% - 40.93%
Standard deviation: 0.00%

Usage Distribution

Low usage (<50%): 1 designs
Medium usage (50-80%): 0 designs
High usage (≥80%): 0 designs

Top 3 Designs by Core Usage

gcd: 40.93%

pin distribution

Pin Distribution Analysis Report

Analyzed 1 design(s) with 34 pin distribution entries
Pin count range: 0 - 33 pins
Unique pin counts: 34

Net Statistics

Average nets per pin group: 20.0
Net count range: 0 - 484
Average net ratio: 0.029
Net ratio range: 0.000 - 0.713

Top 5 Most Common Pin Counts

0 pins: 1 occurrences (avg 0.0 nets)
1 pins: 1 occurrences (avg 0.0 nets)
2 pins: 1 occurrences (avg 484.0 nets)
3 pins: 1 occurrences (avg 115.0 nets)
4 pins: 1 occurrences (avg 20.0 nets)

Vectors analysis

Nets analysis

net wire distribution

Wire Distribution Analysis Report

Analyzed 1 design(s) with 679 total nets

Wire Length Statistics

HPWL - Mean: 18671.6, Min: 1680.0, Max: 176640.0
RWL - Mean: 22389.6, Min: 1680.0, Max: 290640.0

Performance Metrics

Delay - Mean: 0.097, Min: 0.001, Max: 2.841
Power - Mean: 7.788e-07, Min: 1.490e-11, Max: 9.970e-05

Layer Distribution Summary

Layer 2: 40.2% average usage
Layer 4: 38.4% average usage
Layer 6: 14.5% average usage
Layer 8: 6.9% average usage

Per-Design Summary

GCD: 679 nets, Avg HPWL: 18671.6, Avg RWL: 22389.6

net correlation

Metrics Correlation Analysis Report

Analyzed 1 design(s) with 679 total nets

Overall Metrics Statistics

HPWL: Mean=1.867e+04, Std=2.640e+04, Range=[1.680e+03, 1.766e+05]
RWL: Mean=2.239e+04, Std=3.593e+04, Range=[1.680e+03, 2.906e+05]
R: Mean=3.297e+01, Std=4.879e+01, Range=[1.429e+00, 4.081e+02]
C: Mean=7.270e-03, Std=8.781e-03, Range=[6.494e-04, 7.364e-02]
POWER: Mean=7.788e-07, Std=5.567e-06, Range=[1.490e-11, 9.970e-05]
DELAY: Mean=9.739e-02, Std=2.494e-01, Range=[1.397e-03, 2.841e+00]
SLEW: Mean=6.930e-02, Std=2.385e-01, Range=[4.418e-05, 2.896e+00]

Key Correlations

DELAY vs SLEW: 0.990 (positive)
HPWL vs RWL: 0.967 (positive)
RWL vs R: 0.926 (positive)
R vs DELAY: 0.916 (positive)
R vs SLEW: 0.884 (positive)

Per-Design Summary

GCD: 679 nets, Avg HPWL: 18671.6, Avg Delay: 9.739e-02, Avg Power: 7.788e-07

Layer Usage Summary

Layer 2: 40.2% average usage
Layer 4: 38.4% average usage
Layer 6: 14.5% average usage
Layer 8: 6.9% average usage

Patches analysis

patch wire density

Wire Density Analysis Report

Analyzed 1 design(s) with 3,600 total patches

Layer-wise Congestion Summary

Layer-wise Wire Density Summary

Layer 2: Avg=0.062, Max=0.062 (1 designs)
Layer 4: Avg=0.054, Max=0.054 (1 designs)
Layer 6: Avg=0.041, Max=0.041 (1 designs)
Layer 8: Avg=0.020, Max=0.020 (1 designs)

Per-Design Summary

GCD: 3,600 patches, Avg Congestion: -2.513, Avg Density: 0.029
No congestion data

patch feature correlation

Feature Correlation Analysis Report

Analyzed 1 design(s) with 3,600 total patches
Features analyzed: CellDensity, PinDensity, NetDensity, RUDY, Congestion, Timing, Power, IRDrop

Strong Feature Correlations (|r| > 0.5)

NetDensity vs RUDY: 0.714 (positive)
CellDensity vs PinDensity: 0.506 (positive)

Feature Statistics Summary

CellDensity: Avg=4.781e-01, Std=3.262e-01, Range=[0.000e+00, 1.000e+00]
PinDensity: Avg=2.201e+00, Std=2.532e+00, Range=[0.000e+00, 1.400e+01]
NetDensity: Avg=7.281e+00, Std=4.051e+00, Range=[0.000e+00, 1.772e+01]
RUDY: Avg=7.165e-04, Std=4.026e-04, Range=[0.000e+00, 2.436e-03]
IRDrop: Avg=5.785e-05, Std=1.146e-04, Range=[0.000e+00, 3.829e-04]

Per-Design Summary

GCD: 3,600 patches
Cell Density: 0.478, Congestion: -15.077
Timing: nan, Power: nan

patch maps

Spatial Feature Distribution Analysis Report

Analyzed 1 design(s) with 3,600 total patches
Features analyzed: Cell Density, Pin Density, Congestion, Timing, Power, IR Drop, net density, RUDY

Design Layout Summary

GCD: 60 x 60 grid (3,600 patches)

Feature Statistics Across All Designs

Cell Density
Avg Mean: 4.781e-01, Avg Max: 1.000e+00
Avg Hotspot Ratio (>90th percentile): 10.0%
Pin Density
Avg Mean: 2.201e+00, Avg Max: 1.400e+01
Avg Hotspot Ratio (>90th percentile): 8.9%
Congestion
Avg Mean: -1.508e+01, Avg Max: -1.000e+00
Avg Hotspot Ratio (>90th percentile): 8.5%
Timing
Avg Mean: nan, Avg Max: nan
Avg Hotspot Ratio (>90th percentile): 0.0%
Power
Avg Mean: nan, Avg Max: nan
Avg Hotspot Ratio (>90th percentile): 0.0%
IR Drop
Avg Mean: 5.785e-05, Avg Max: 3.829e-04
Avg Hotspot Ratio (>90th percentile): 10.0%
net density
Avg Mean: 7.281e+00, Avg Max: 1.772e+01
Avg Hotspot Ratio (>90th percentile): 10.0%
RUDY
Avg Mean: 7.165e-04, Avg Max: 2.436e-03
Avg Hotspot Ratio (>90th percentile): 10.0%

Per-Design Detailed Summary

GCD (60x60)
Max Congestion: -1.000, Max Timing: nan, Max Power: nan
Most non-uniform feature: net density (variance: 1.640e+01)

Paths analysis

path delay

PATH DELAY ANALYSIS REPORT

OVERALL STATISTICS

Total designs analyzed: 1
Total paths analyzed: 136

DELAY STATISTICS SUMMARY

Instance Delay - Mean: 1.385, Std: 0.000
Net Delay - Mean: 0.002, Std: 0.000
Total Delay - Mean: 1.386, Std: 0.000

PER-DESIGN SUMMARY

Design: GCD (gcd)

Paths: 136
Instance Delay: 1.385 ± 0.900 (median: 1.233)
Net Delay: 0.002 ± 0.002 (median: 0.001)
Total Delay: 1.386 ± 0.901 (median: 1.234)

path stage delay

STAGE ANALYSIS REPORT

OVERALL STATISTICS

Total designs analyzed: 1
Total paths analyzed: 136

STAGE STATISTICS SUMMARY

Average Stage Count - Mean: 11.96, Std: 0.00
Stage Range - Min: 4.0, Max: 22.0
Total Delay - Mean: 1.386, Std: 0.000

PER-DESIGN SUMMARY
Design: GCD (gcd)

Paths: 136
Stage Count: 11.96 ± 7.97 (median: 12.00)
Stage Range: 4.0 - 22.0
Average Total Delay: 1.386

← 报告分析

workspace summary - gcd - sky130

# Technology information

# foundry configs

# flows

# basic information

# flow status

# floorplan

# PDN

# fixFanout

# place

# CTS

# optDrv

# optHold

# legalization

# route

# drc

# filler

# Design analysis

# Design features

# design statis

# cell type

# core usage

# pin distribution

# Vectors analysis

# Nets analysis

# net wire distribution

# net correlation

# Patches analysis

# patch wire density

# patch feature correlation

# patch maps

# Paths analysis

# path delay

# path stage delay

用开放中间状态继续构建

Technology information

foundry configs

flows

basic information

flow status

floorplan

PDN

fixFanout

place

CTS

optDrv

optHold

legalization

route

drc

filler

Design analysis

Design features

design statis

cell type

core usage

pin distribution

Vectors analysis

Nets analysis

net wire distribution

net correlation

Patches analysis

patch wire density

patch feature correlation

patch maps

Paths analysis

path delay

path stage delay