Conference · ISEDA

Accurate Timing Path Delay Learning using Feature Enhancer withEffective Capacitance

He Liu, Shengkun Wu,Simin Tao, Biwei Xie, Xingquan Li*,and Ge Li. “ · 2000

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研究要点

围绕时序与时钟结构的预测或优化，可对接 iSTA / iCTS / AiSTA 的工程路径。

完整条目

He Liu, Shengkun Wu,Simin Tao, Biwei Xie, Xingquan Li*,and Ge Li. “Accurate Timing Path Delay Learning using Feature Enhancer withEffective Capacitance”, In Proceedings of IEEEInternational Symposium of EDA (ISEDA), 2023.

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