Skip to content
Conference · ISEDA

Accurate Timing Path Delay Learning using Feature Enhancer withEffective Capacitance

He Liu, Shengkun Wu,Simin Tao, Biwei Xie, Xingquan Li*,and Ge Li. “ · 2000

Open PDF / link →Matrix
iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model

Why it matters

He Liu, Shengkun Wu,Simin Tao, Biwei Xie, Xingquan Li*,and Ge Li. “ Accurate Timing Path Delay Learning using Feature Enhancer withEffective Capacitance ”, In Proceedings of IEEEInternational Symposium of EDA (ISEDA), 2023.

Citation entry

He Liu, Shengkun Wu,Simin Tao, Biwei Xie, Xingquan Li*,and Ge Li. “Accurate Timing Path Delay Learning using Feature Enhancer withEffective Capacitance”, In Proceedings of IEEEInternational Symposium of EDA (ISEDA), 2023.

Product links

Use the related capabilities to jump from this paper into the toolchain or AiEDA modules.