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LESSON

EDA Course - Week1

Learning Notes : Next, we are about to formally start learning EDA. Understand the EDA process, what are the purposes and reference indicators of each link. For the project introdu

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DAY1: Introduction to EDA Basics

Learning Notes: Next, we are about to formally start learning EDA. Understand the EDA process, what are the purposes and reference indicators of each link. For the project introduction, you can first browse the iEDA Bilibili video accountopen in new window. If you have any questions or ideas during the learning process, you can also contact and ask the teachers and students of the relevant projects of iEDA.

To prevent forgetting after reading, when reading books, it is recommended to sort out the main EDA process before reading and construct a mind map; then supplement the details during the reading process.

1. Specific Requirements

Learning Content

Study Chapter 1 and Chapter 2 of "Physical Design of Digital Integrated Circuits" and Chapter 1 of "Physical Design of VLSI Circuits: From Graph Partitioning to Timing Convergence".

  1. Understand the basic process of chip design, the front-end (requirement formulation, architecture design, functional design), and the back-end (logic synthesis, physical design, sign-off analysis, physical verification)
  2. Understand the VLSI process, tools, and sub-steps of physical design.
  3. Standard format files for chip design, including Verilog, LEF/DEF, Liberty, SPEF, SDC, etc.

2. Learning Outcomes Presentation

Sort out the reading notes of the books and paste the note link into the daily record.

3. Reference Materials

  • Book recommendations: "Physical Design of VLSI Circuits", "Physical Design of Digital Integrated Circuits".
  • Image materialsopen in new window: "EDA Backend Data Flow Diagram_Guo Fan.png", "EDA Backend Flowchart_Wu Zhendong.png", "EDA Backend Process Mind Map_Wang Rui.png".

DAY2: Introduction to Logic Synthesis

1. Specific Requirements

Learning Content

  1. Logic compilation, understand the process of compiling the hardware programming language Verilog to the internal logic diagram GTech
    • "Logic Synthesis in a Nutshell" (Chapter 1)
    • "Synthesis and Optimization of Digital Circuits" DT1, DT2
  2. Logic representation, understand the representation methods of logic including BDD, AIG, MIG, etc.
  3. Logic optimization, understand basic concepts and methods such as Boolean optimization, logical equivalence, complex logic decomposition, state machine optimization, etc.
    • "Logic Synthesis in a Nutshell" (Chapter 3)
    • "Synthesis and Optimization of Digital Circuits" DT5, DT6
    • Paper DAG-Aware AIG Rewriting A Fresh Look at Combinational Logic Synthesis (Optional)
    • Paper Delay optimization using SOP balancing (Optional)
  4. Technology mapping, the process of mapping the logic diagram to the technology gate circuit, as well as concepts such as Cut and SuperGate in the technology mapping, area, timing and power optimization methods
    • "Electronic Design Automation for IC Implementation, Circuit Design", Chapter 2 Logic Synthesis, Chapter 3 Power Analysis and Optimization from Circuit to Register-Transfer Levels
    • "Logic Synthesis in a Nutshell" (Chapter 4)
    • Paper Cut ranking and pruning: enabling a general and efficient FPGA mapping solution (Optional)
    • Paper Combinational and sequential mapping with priority cuts (Optional)

2. Learning Outcomes Presentation

  • Sort out the reading notes of the books and share the note link in the daily record.

3. Reference Materials

DAY3: Introduction to FloorPlan and Placement

1. Specific Requirements

Learning Content

  1. Basic knowledge of floorplan, including partitioning, IO planning, power network planning, macrocell placement, etc. Specifically, you can study
    - "Physical Design of VLSI Circuits: From Graph Partitioning to Timing Convergence" Chapter 3
    - "Handbook of Algorithms For Physical Design Automation": Part III (Optional)
    - "Electronic Design Automation": Chaper 10
  2. Basic knowledge of placement, including the concept of hypergraph, wire length model, density model, optimization methods, etc. You can study the books
    - "Handbook of Algorithms For Physical Design Automation" Part Ⅳ
    - "Electronic Design Automation" Chaper 11
    - "Physical Design of VLSI Circuits: From Graph Partitioning to Timing Convergence" Chapter 4 Global and Detailed Placement.
  3. Basics of optimization/combinatorial optimization, you can study the book "Combinatorial optimization. Theory and algorithms" (Optional)

2. Learning Outcomes Presentation

  • Sort out the reading notes of the books and share the note link in the daily record.

3. Reference Materials

DAY4: Introduction to Clock Tree Synthesis

1. Specific Requirements

Learning Content

  1. Basics of clock tree synthesis, including the composition of the clock tree (clock source, clock buffer, clock inverter), clock tree topology (Tree, Mesh, etc.), common algorithms for clock tree synthesis (Zero Skew, Useful Skew, etc.)
    "Electronic Design Automation: Synthesis, Verification, and Test " CHAPTER 13 Synthesis of clock and power/ground networks
    BIU Lectureopen in new window
    Modern CTS Summary Paper: Performance Analysis on Skew Optimized Clock Tree Synthesis
  2. Design principles of CTS, Ultimate Guide: Clock Tree Synthesisopen in new window
  3. Commercial tools (Innovus) Design Flowopen in new window (Optional)
  4. DME, "A computer aided design software module for clock tree synthesis in very large scale integration design" (Optional)
  5. Timing calculation (Optional)
    Linear Delay: Timing characterization of clock buffers for clock tree synthesis
    PERI: Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
    Bakoglu Metric: Circuits, interconnections, and packaging for VLSI

2. Learning Outcomes Presentation

  • Sort out the reading notes of the books and share the note link in the daily record.

3. Reference Materials

DAY5: Introduction to Routing

1. Specific Requirements

Learning Content

  1. Learn the basic concepts of routing, including Routing Track (Column), Gcell, Steiner Tree, common DRC rules (Short, Space, Min Area), etc.
  2. Learn the basic process of routing, including Global Routing, Detail Routing (including Track Assignment, Pin Access, Rip-Up and Reroute, etc.)
  3. Learn the basic algorithms of routing, maze algorithm, pattern routing, AStar algorithm.

You can study the following chapters:

  • Chapters 5 and 6 of "Physical Design of VLSI Circuits: From Graph Partitioning to Timing Convergence"
  • Chapter 5 of "Physical Design of Digital Integrated Circuits", Appendix 7 Introduction to LEF Document, Appendix 9 Introduction to DEF Document

2. Learning Outcomes Presentation

  • Sort out the reading notes of the books and share the note link in the daily record.

3. Reference Materials

DAY6 - DAY7: Static Timing Analysis and Optimization

1. Specific Requirements

Learning Content

  1. Basic knowledge of digital circuits, including MOSFET, combinational logic circuits, sequential logic circuits. You can study Chapters 1-5 of the book "Digital Circuits and Logic Design".
  2. Verilog language learning, including Module, Port, Netlist. You can study Chapters 1-6 of the book "Verilog HDL Digital Design and Synthesis".
  3. Basic concepts of timing, including Delay, Transition Time (Slew), Skew, Clock Domain, Cell Library, Slack, Timing Arc, Timing Path. You can study Chapters 1-2 of the book "Static Timing Analysis for Nanometer Designs".
  4. Delay calculation (Delay Calculation), including Cell Delay, SPEF, Interconnect Delay calculation methods. You can study Chapters 3-5 of the book "Static Timing Analysis for Nanometer Designs". In addition, you can read supplementary books and papers on the calculation methods of model order reduction such as AWE and Arnodi (Optional).
  5. Timing constraints (SDC), including create_clock, set_input_delay, set_output_delay, set_max_fanout, set_max_transition, etc. You can study Chapter 7 of the book "Static Timing Analysis for Nanometer Designs".
  6. Timing propagation and analysis (STA), including Setup/Hold, Multicycle Path, Recovery/Removal. You can study Chapter 8 of the book "Static Timing Analysis for Nanometer Designs".
  7. Timing analysis and optimization methods (Gate Sizing, Buffering, etc.), you can study Chapter 8 of the book "Physical Design of VLSI Circuits: From Graph Partitioning to Timing Convergence": Have a preliminary understanding of timing convergence and timing optimization techniques

2. Learning Outcomes Presentation

  • Sort out the reading notes of the books and share the note link in the daily record.

3. Reference Materials