EDA tooling built for
IC design Agents
40+ headless EDA tools, one unified database, and a full Agent API—so your LLM can drive chip design end to end. From RTL to GDS, every step can be called, observed, and decided by an Agent.
# Agent calls EDA tools directly $ agent.call("iPL.place", { design: "aes_core", effort: "standard", intent: intent_ref }) → PlacementResult { hpwl: 1245678, density: 0.72, ... }
Four-layer architecture, Agent-Native by Design
From the unified data base to Agent services—every layer is designed to be called by LLMs.
iDB · Platform · Interface · Evaluation
iDB is the hub—every tool shares one design state. A standard Interface makes each capability a first-class API, with evaluation measuring tools and Agents.
For tool authors: one interface joins the ecosystem. For Agent authors: one shared semantic space.
┌──────────────────────────────────────┐
│ Interface │
│ (Python / MCP / Tcl standard interface) │
├──────────────────────────────────────┤
│ iDB │
│ Unified design DB · shared in-memory state │
├──────────────────────────────────────┤
│ Platform · Evaluation │
│ Flow orchestration Quality metrics │
└──────────────────────────────────────┘
Shared design state · API first-class
22 RTL→GDS point tools
Synthesis, floorplan, power, place, clock, optimize, route, timing, power, DRC, extraction—each tool is headless with a unified Agent API. Call them alone or orchestrate with iFlow.
Every tool is directly callable by Agents and returns structured results.
RTL → iMap → iNO → iFP → iPDN
→ iPL → iCTS → iTO → iRT
→ iSTA → iPA → iDRC → iRCX
↓
GDSII + reports
Each tool is directly callable by Agents
Runtime · Observer · Router · Oracle · Factory
Runtime manages experiments and state; Observer watches tool runs; Router picks models by task; Oracle supplies ground truth; Factory produces training samples.
Make Agent experiments manageable, state observable, and model routing smart.
┌──────────────────────────────────────┐ │ Runtime Observer │ │ Experiments Observe │ ├──────────────────────────────────────┤ │ Router Oracle │ │ Route models Reference │ ├──────────────────────────────────────┤ │ Factory │ │ Samples │ └──────────────────────────────────────┘ Experiments · observation · model routing
Planner · Intent · Verify · Tech · Memory · Bridge
Planner turns natural-language intent into tool sequences; Intent captures constraints; Verify checks intermediates; Tech injects process knowledge; Memory keeps context; Bridge connects external models and knowledge bases.
Plan, intent, verify, knowledge—so Agents truly understand chip design.
┌──────────────────────────────────────┐ │ Planner Intent Verify │ │ Plan Intent Verify │ ├──────────────────────────────────────┤ │ Tech Memory Bridge │ │ Tech Memory Bridge │ └──────────────────────────────────────┘ Plan · intent · verify · knowledge
12 core EDA tools
Full flow from front-end synthesis to back-end signoff—each tool is directly callable by Agents.
Three steps to let your Agent drive chip design
From picking tools to wiring your LLM—one Agent API keeps the path smooth.
Pick tools
Browse 40+ Agent-native tools—22 EDA point tools covering RTL→GDS, plus Agent infra and services. Each tool ships with clear API docs and call examples.
EDA tools (22) Infra (8) Services (10+) ───────────────────────────────────────────── iMap iNO iFP Runtime Planner iPDN iPL iCTS Observer Intent iTO iRT iSTA Router Verify iPA iDRC iRCX Oracle Tech iFV iEval ... Factory ... Memory ...
Call the API
One Agent API across Python, MCP, and Tcl. Same semantics, same return shape—results are ready for Agents to consume.
from ieda import Agent
agent = Agent("aes_core")
result = agent.call("iPL.place",
effort="standard")
# → PlacementResult { hpwl: 1245678,
# density: 0.72, ... }
{
"tool": "iPL.place",
"params": {
"design": "aes_core",
"effort": "standard",
"intent": "intent_ref"
}
}
→ PlacementResult { ... }
iPL::place -design aes_core \
-effort standard \
-intent $intent_ref
# → PlacementResult { hpwl 1245678
# density 0.72 ... }
Integrate your Agent
Connect your LLM to the iEDA Agent API. Planner decomposes natural-language goals into tool calls; Runtime manages experiments; Observer feeds intermediate results—so your Agent can drive the flow like a seasoned engineer.
User: "Place aes_core with standard constraints"
↓
┌─────────────────────┐
│ Your LLM │
└────────┬────────────┘
↓
┌─────────────────────┐
│ iEDA Agent API │
│ Planner → iPL │
│ Observer → Verify │
└─────────────────────┘
↓
PlacementResult + feedback
Silicon-proven tape-outs
The toolchain has taped out chips across process nodes; silicon data keeps feeding engineering and datasets.
110nm validation chip
Full-flow bring-up; first silicon loop for the iEDA toolchain from RTL to GDS.
28nm SoC tape-out
Advanced-node validation; timing closure and power opts confirmed on silicon.
28nm accelerator chip
Domain-specific accelerator full flow; silicon data feeds tool algorithms.
110nm mixed-signal chip
Digital+analog mixed-signal flow validation, expanding toolchain coverage.
28nm research tape-out
Continuous iteration—silicon data drives tool improvements and datasets.
AI for EDA research
ML and foundation models for logic synthesis, physical design, and layout representation—tied to the open toolchain.
AiEDA: Design-to-Vector Library
Open AI-assisted design library exporting design state as learnable vectors.
Details →iPCL: Pre-training for Chip Layout
Layout pretraining paradigm linking representation, generation, and evaluation.
Details →All papers
48+ journal and conference papers across AI-for-EDA topics; open details or the PDF.
Browse all papers →Talent training & knowledge → Academy
Courses and hands-on tutorials are no longer part of the product narrative. Enter via Academy when you need systematic learning (hosted on the same origin for now; may move later).
Ready to let your Agent drive chip design?
40+ headless EDA tools, a unified database, and a full Agent API—from RTL to GDS, your LLM can call every step.