1 Problem background
Wire length prediction delay refers to using EDA tools to estimate the length of the connection during the chip design process and further predict the delay of signal transmission. The length of different signal lines will affect the signal transmission delay. Longer signal lines increase the time required for signal transmission, which can lead to timing issues and performance degradation. Therefore, delay prediction after the Detail routing stage on the line length in the Global Routing stage can help evaluate and optimize the performance of signal transmission.
Line length prediction delay is usually performed through the following steps:
● Build a model: Use EDA tools to establish a mathematical model of signal transmission delay based on the physical layout information and circuit parameters of the chip design. These models usually consider the effects of resistance, capacitance, process factors, etc. on signal transmission.
● Estimated line length: Based on the physical layout information and circuit connection relationships, the length of each interconnection line is estimated through the GR stage of the EDA tool, including the total length of the net and the length from the driver to each load in each net.
● Calculate delay: Substitute the GR estimated line length and other auxiliary features into the model, and use EDA tools to calculate the signal transmission delay after the DR stage. This can include comprehensive considerations of propagation delays, cable delays, signal interference, and other factors.
● Analysis and optimization: Perform signal integrity and timing analysis based on the predicted delay results. If there are timing problems or the performance does not meet the requirements, optimization measures can be taken, such as re-planning the layout, adjusting the drive current, modifying the clock distribution, etc.
2 Problem description
For a given chip layout and circuit connection relationship, it is necessary to estimate the length of each signal line and other factors that affect delay, including capacitance, resistance, slew, etc., and further predict the delay of signal transmission.
1、Implement requirements: Follow the module division of the iEDA platform to implement a line length prediction network model to complete the function: divide the given input data set into a training set and a test set, and use Pytorch for data preprocessing and reading, then design the network model, train the network model, design the loss function, output the regression prediction results and evaluate the accuracy.
2. Methods to solve the problem of line length prediction delay usually include the following steps：
● Calculate the geometric length of each signal line in the Global Routing stage based on chip layout information and circuit connection relationships. This can be estimated based on methods such as coordinate differences or Manhattan distance.
● Consider physical properties such as resistance and capacitance, and combine process parameters and actual circuit models to establish a mathematical model of signal transmission delay. This model can take factors such as propagation delay, cable delay, and signal interference into account. The physical characteristics and electrical characteristics information of each net are obtained through the internal iSTA tool, and used together with the length of the signal line as the input characteristics of the delay prediction model.
● Use EDA tools or self-developed algorithms to build a machine learning model or neural network model, as well as the line length in the Global Routing stage, to obtain the predicted delay of each signal line after Detail Routing.
● Analyze and evaluate predicted delays to check whether timing requirements and performance targets are met. If there is a problem, the delay performance can be improved by adjusting the layout, optimizing the signal path, modifying the drive current, etc.
3 input and output
Algorithm input
- The task is to predict the delay from the driver to each load in each net after DR based on the line length in the GR stage. Therefore, the input of the algorithm is the factors that affect the delay, including line length, slew, capacity, etc. Which features are most effective need to be judged by correlation analysis.
algorithm output
● Estimate the length of each signal line and calculate the corresponding signal transmission delay. The output can be a list or data structure containing each signal line and its corresponding length and delay.
4 Evaluation indicators
● Latency Delay/Accuracy: Measures the difference between predicted latency and actual latency. It can be measured by mean absolute error or mean relative error.