CATALOG
Algorithm
Algorithm — learning path connecting EDA fundamentals to open practice.
In this section
01
A1 — Placement legalization
The layout process can be divided into three stages: Global Placement, Legalization, and …
02A2 — Functional-vector timing fault simulation
Fault simulation is an important step in chip testing and an important part of the test v…
03A3 — Incremental timing optimization
Chips play a key role in electronic devices such as mobile phones, computers, and automob…
04A4 — FPGA technology mapping & optimization
With the increasing complexity of chip design and the continuous development of advanced …
05A5 — GPU-accelerated placement optimization
Software environment: gcc7.5.0, g++7.5.0, glibc2.27, python3.7, cuda-driver.
06A6 — GPU-accelerated equation solving
There are a large number of differential equations, partial differential equations, and l…
07A7 — Automatic VLSI cell placement
Background Very Large Scale Integration (VLSI) integrates a large number of circuit units…