1 Problem background
Capacitance extraction refers to the process of using EDA tools to conduct electrical analysis on the electrostatic balance system composed of metal conductors and dielectrics during the chip design process, and to solve the capacitance matrix composed of the system. Parasitic capacitance is crucial in steps such as delay estimation, power consumption calculation, and crosstalk analysis. With the advancement of technology, interconnection lines have become narrower and thinner, through-holes have increased, wiring density per unit area has increased significantly, and the capacitance effect between interconnection lines has increased significantly. Accurate and fast large-scale capacitance extraction technology has become indispensable.
Large-scale capacitance extraction, also known as pattern matching (Pattern Matching). The common steps are divided into two:
Build a Pattern Library: Based on the integrated circuit process parameters, various possible interconnect structures are listed, and then two-dimensional or three-dimensional accurate capacitance extraction is performed on these tens of thousands of medium-sized structures (called Patterns). The calculated capacitance data of these structures are collected and empirical formulas are fitted, or a lookup table is constructed.
Layout parasitic parameter extraction: Correspond the modeling results of the interconnection lines to the parameters in the Pattern, call the empirical formula or use the lookup table to interpolate the query to obtain the corresponding capacitance value.
As semiconductor processes become increasingly complex, the accuracy of pattern matching is challenged. In three-dimensional space, since the parameters of interconnections are very large, it is almost impossible to construct appropriate lookup tables and effective empirical formulas. A method to describe the geometry of interconnections and their dielectric environment through point clouds has been proposed. Exploration of three-dimensional pattern matching is carried out through this form of point cloud expression.
2 Problem description
The conductor geometry and dielectric environment of the local area of the chip are given in the form of a point cloud, and the precise capacitance value of such a three-dimensional capacitor sample needs to be estimated.
1. Implement requirements:
- Follow the module division of the iEDA platform to implement a line length prediction network model to complete the function: divide the given input data set into a training set and a test set, and use Pytorch for data preprocessing and reading, then design the network model (can be designed as a CNN model, Transformer, etc.), train the network model, design the loss function, output the regression prediction results and evaluate the accuracy.
2. The method of capacitance prediction through point cloud usually includes the following steps:
- Feature processing: Combined with the characteristics of the capacitive task itself, specific processing is performed on the feature channels in the point cloud.
- Point selection sampling: Different points have different importance for capacitance calculation. An appropriate sampling strategy can significantly improve the accuracy of the model.
- Data enhancement: Due to the flexibility of wiring, appropriate symmetry, translation, and rotation generate more data, which helps the model explore more input space.
- Network design: A reasonable network design can take into account the characteristics of the capacitance problem and make full use of the information contained in the point cloud.
3 input and output
Algorithm input
- 3D Capacitance Dataset
Three-dimensional capacitor sample overview file and point cloud file.
pc_annotation.csv - 3D capacitor sample overview file
variable name Description point_cloud_path point cloud path conductor_num The number of conductors contained in the original 3D sample point_num Point cloud size, number of points electrode1_point_num Point cloud size generated by the main conductor electrode2_point_num Point cloud scale generated by target environment conductor cap_type Capacitance type: total capacitance or coupling capacitance coupling cap Capacitance reference value, label v1_x The absolute position x coordinate of the original sample in the layout v1_y The absolute position y coordinate of the original sample in the layout v1_z The absolute position z coordinate of the original sample in the layout dx The x-direction size of the original sample dy The y-direction size of the original sample dz The z-direction size of the original sample timestamp Point cloud file generation time solver_time Time to calculate 3D capacitance sample via solver w500l2_1_C_0_0.txt - Point cloud file example
symbol Description Coordinate x Coordinate y Coordinate z normal vector x component normal vector y component normal vector z component dielectric near point class The source of the point Select channel Demo:line 1 : 432.715, 171.114, 0.5879, 1, 0, 0, 4.06, 1, 0
- The coordinates of a point in the map are (432.715, 171.114, 0.5879)
- Its local normal vector of the generating surface is (1, 0, 0)。
- The area near it is filled with a relative dielectric constant of 4.06 dielectric, if there is no dielectric inside the conductor.
- His generation source code is 1。
- The selection channel for this point is 0, is set based on non-target environmental conductors.
- Please refer to the channel selection details Point cloud features based on Gauss’ theorem
algorithm output
- The elements in the capacitance matrix and the capacitance value are determined according to the selected channel.
4 Evaluation indicators
- Remember each point cloud sample as:
- Error calculation formula:
- Model accuracy with error within 5%:
- Model accuracy with error between 5% and 10%:
- Model accuracy with error greater than or equal to 10%:
- Average error:
- Maximum error:
- Standard deviation of error: