1 Problem background
For the design of high-performance chips, timing closure is the most critical requirement. In order to obtain a chip design with accurate timing, timing analysis tools need to be used at various stages of physical design to analyze timing margins to guide the chip design process. Therefore, accurate timing analysis results are crucial for iterative optimization of chip-guided design and achieving better timing closure results. For the widely used timing path delay calculation method, the unit delay is calculated through the look-up table (LUT) method, and the interconnection line delay is calculated using the classic Elmore model. The delay of each timing path is obtained by accumulating the delays of units and interconnect lines at each level in the timing path. Slew calculation errors will gradually accumulate during the propagation process from driver to load in the timing path, and unit delay and interconnection line delay will also gradually accumulate errors during this process. Since the method of analyzing delay is relatively simple and does not consider the influence of crosstalk, noise and other factors, there is a certain deviation from the delay analysis results of commercial tools. In order to obtain more accurate results, this deviation is corrected through machine learning methods.
2 Problem description
The process of timing calibration mainly includes the following steps: (1) Extracting features related to timing path delay; (2) Constructing label data; (3) Model selection and construction; (4) Model training and inference.
● Extract features related to timing path delays: Timing path delay includes unit delay and interconnection line delay. Therefore, when selecting features, key factors that will affect the unit delay and interconnection line delay should be selected: the unit delay is obtained through a two-dimensional lookup table, and the index is the input Slew and the output load capacitance. The value of Slew affects the driving strength of the load unit on the current timing path, and the load capacitance also affects the output Slew when slew propagates in the unit. The calculation of interconnection line delay uses the Elmore model, which mainly contains resistance and capacitance information. At the same time, different unit types and different unit ports will affect the function and driving strength of the unit. The flip polarity of the signal is different. Different delay tables need to be searched in the two-dimensional lookup table. Therefore, the signal flip polarity is also a factor that needs to be considered. To sum up: the selectable features include: input transition time, output transition time, load capacitance, signal polarity (rising/falling), unit type, unit port name, resistance, capacitance, and timing path delay calculated by iSTA.
| Feature name | Description |
|---|---|
| Input transition | Enter conversion time |
| Output transition | Output conversion time |
| load capacitance | load capacitance |
| Signal polarity(rise/fall) | Signal polarity (rising/falling) |
| Cell type | Unit type |
| Cell port name | Unit port name |
| incremental time | incremental delay |
| Arrival time | Arrival time |
| Path delay(LUT+Elmore) | iSTA analysis latency |
● Build label data: When selecting labels, select the delay information reported by the commercial tool Prime Time as the label. Because when building features, we can calculate the timing path delay through the internal iSTA tool. Through data analysis, it is found that the timing path delay obtained by PT analysis and the results obtained by iSTA have large variances, but the ratio of the PT results and iSTA tends to be stable, making it easier to converge during training. Therefore, the ratio between the two is selected as the label.
● Model selection and construction：
(1) Since the constructed features are two-dimensional tabular data, traditional machine learning models can be selected when selecting models, such as random forest, lightGBM, and XGBoost. It can be built using the Scikit-learn machine learning library.
(2) Each timing path can be modeled as a sequence. Each pin node contains several features, and the Transformer/LSTM/RNN + MLP model in the sequence processing task can be used. It can be built using the Pytorch machine learning library.
● Model training and inference ：
(1) During the model training process, due to the large training data set, batch training needs to be used, but the length of each timing path is different. At this time, it needs to be filled to a uniform length through the Pad method.
(2) Use a ratio of 8:2 for division, 80% for training and 20% for verification. Verification between different designs under the same process node is also required.
3 input and output
Algorithm input
- When reasoning about the delay of each timing path, the input data is a two-dimensional tensor composed of the characteristic data in each timing path.
algorithm output
- The output of the model is the ratio of the real value to the delay value calculated by iSTA. Therefore, the product of the model output result and the delay value of the path calculated by iSTA is the delay value after calibration.
4 Evaluation indicators
- When using neural networks for training, RMSE or MSE is generally selected as the loss function;
- The accuracy of the model can be measured using indicators such as R2, MSE, MAE, and MRE;
- The accuracy of the model is measured by analyzing the proportion of paths with errors within 1%, 3%, and 5% of the PT results of commercial tools.