Core capabilities
- Minimal fix: Change only logic/physical cells on violating paths while preserving completed work elsewhere.
- Timing ECO: Auto-fix setup/hold violations with buffer insertion, cell sizing, and local logic restructuring.
- DRC ECO: Local re-route or metal fill for post-route DRC violations.
- Workflow integration: Works with iSTA, iTO, and iDRC—ingests violations and emits fix proposals.
- Agent-ready: Python API accepts violation lists and returns a fixed design snapshot reference.
Agent calling patterns
eco = client.call("iECO.fix",
design_ref="snap_7f3a",
violations=timing_violations
)
# eco.modified_design_ref → str (new snapshot reference)
# eco.patch_count → int (cells/nets changed)
# eco.preserved_stats → dict (preservation stats)
Input / output contract
| Direction | parameter | Type | Description |
|---|---|---|---|
| Input | design_ref | str | Current design snapshot reference |
| Input | violations | list | Violation list from iSTA/iDRC with path/coords/type |
| Input | strategy | str (optional) | Fix strategy: buffer_insert | cell_swap | reroute_local |
| Output | modified_design_ref | str | Fixed design snapshot reference |
| Output | patch_count | int | Cells/nets actually modified |
| Output | preserved_stats | dict | Preservation rate by stage (placement, routing, timing) |
Role in the flow
01 Synth
iMap
Logic synthesis & tech mapping
02 Physical design
iFP · iPL · iCTS · iRT
Full place & route flow
03 Analysis
iSTA · iDRC
Timing & design rule check
04 ECO fix
iECO · iTO
Localized ECO & optimization
iECO closes the fix loop after iSTA/iDRC report violations—repairing with minimal change instead of full re-place & route.
Related resources
- iTO — Timing optimization: Full timing optimization; ECO is its localized fix mode.
- iSTA — Static timing analysis: Violation source and primary ECO input.
- iDRC — Design rule check: Source of DRC violations.
- EDA tools overview: Map of all 22 point tools.