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iEDA.ai — rtl2gds
# iEDA open design stack
$ ./iEDA -script iFlow/run_iEDA.tcl
[iDB ] load shared state      ok
[iPL ] placement              ok
[iRT ] routing                ok
[iSTA] timing                 ok
→ design state ready for AI
iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model
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