iMap · Logic synthesis

Core capabilities

iMap is the first stop in iEDA's RTL→GDS flow: it converts register-transfer-level (RTL) descriptions into a gate-level netlist for the target library. Internally it uses an AIG (And-Inverter Graph) IR and supports both FPGA and ASIC mapping. For Agents, the key value is exposing synthesis intermediate state—cut sets, AIG structure, and area/depth estimates—enabling smarter decisions than fixed scripts.

Agents typically use iMap for: synthesis strategy exploration—try depth-oriented vs. area-oriented mapping and pick the better QoR; library adaptation—map against multiple target libraries and auto-select by area/timing/power trade-offs; cut-level optimization—give critical nodes larger k-feasible cuts and tighten cuts elsewhere to save area; logic restructuring guidance—find rewrite/balance subgraphs in the AIG, re-map the optimized AIG, and compare QoR.

In AI-assisted flows, iMap works with AiMap (learning models): AiMap learns how mapping choices correlate with PPA and predicts synthesis parameters; Agents inject AiMap recommendations into iMap calls, run synthesis, and verify—closing a predict→execute→verify→feedback loop.

iMap tech mapping uses a priority-cut framework with k-feasible cut enumeration, cut function computation (truth tables), cut domination pruning, and choice computation to remove structural bias. Internals are opaque to Agents, but Agents can tune k, priority-cut limits, and area-flow vs. edge-flow weights. Agents can also inspect the mapped LUT network, spot redundant or suboptimal cone coverage, and trigger local area/edge recovery.

Agent calling patterns

# Agent calls iMap for logic synthesis
from ieda_client import IEDAClient

client = IEDAClient()

# Basic synthesis — default effort
result = client.call("iMap.synthesize",
    design_ref="snap_7f3a",
    tech="sky130",
    effort="standard")

# Constrained synthesis — Agents can inject SDC
result = client.call("iMap.synthesize",
    design_ref="snap_7f3a",
    tech="sky130",
    effort="aggressive",
    constraints={ "clock_period": 2.5, "max_area": 50000 },
    optimization_goals=["area", "timing"])

# Agent reads results and picks next strategy
print(f"Netlist: {result['netlist_ref']}")
print(f"Area:   {result['area']} um²")
print(f"Gates:  {result['gate_count']}")

{
  "tool": "iMap.synthesize",
  "arguments": {
    "design_ref": "snap_7f3a",
    "tech": "sky130",
    "effort": "standard"
  }
}

# Tcl interactive synthesis flow
iMap::set_technology sky130
iMap::read_design snap_7f3a
iMap::set_effort standard
iMap::synthesize -design snap_7f3a -tech sky130 -effort standard
iMap::report_area
iMap::report_timing
iMap::write_netlist -format verilog -output snap_7f3a_synth.v

Input / output contract

Role in the flow

RTL (Verilog/VHDL)
        │
        ▼
  ┌─────────────┐
  │   iMap      │  ← Current tool: Logic synthesis & tech mapping
  │  Synthesis   │
  └──────┬──────┘
         │  netlist
         ▼
  ┌─────────────┐
  │    iNO      │  Netlist optimization (fanout repair, buffer insertion)
  │  Netlist optimization │
  └──────┬──────┘
         │
         ▼
  ┌─────────────┐
  │    iFP      │  Floorplanning (die/core/IO/macros)
  │  Floorplan   │
  └──────┬──────┘
         │
    ··· Later steps ···
         │
         ▼
       GDSII

Related resources