Paper matrix
48 works. Filter, then open a detail page or source link.
DD-DeepONet: A domain decomposition DeepONet framework for PDEs on structured domains with geometry and physics variatio
Bo Yang, Xingquan Li, Jie Zhao, Ying Jiang*. DD-DeepONet: A domain decomposition DeepONet framework for PDEs on structured domains with geometry and physics variations ,
Details →CircuitFlow: Learning Dynamic Representations for Logic Optimization
Miao Liu , Xinhua Lai , Liwei Ni , Xingyu Meng , Rui Wang , Junfeng Liu , Xingquan Li*, Jungang Xu*. CircuitFlow: Learning Dynamic Representations for Logic Optimization
Details →SensTDDP: A Timing Sensitivity Analysis Framework with Application to Timing-Driven Detailed Placement
Qiang Yang, Jiahui Li, Hongxi Wu, Xingquan Li, Bei Yu, Wenxing Zhu*. SensTDDP: A Timing Sensitivity Analysis Framework with Application to Timing-Driven Detailed Placemen
Details →A Survey of Machine Learning Approaches in Logic Synthesis
Miao Liu, Liwei Ni, Junfeng Liu, Xingyu Meng, Rui Wang, Xiaoze Lin, Xinhua Lai, Xingquan Li*, and Jungang Xu*. A Survey of Machine Learning Approaches in Logic Synthesis
Details →AiEDA: An Open-Source AI-Aided Design Library for Design-to-Vector
Yihang Qiu, Zengrong Huang, Simin Tao, Hongda Zhang, Weiguo Li, Xinhua Lai, Rui Wang, Weiqiang Wang*, Xingquan Li*. AiEDA: An Open-Source AI-Aided Design Library for Desi
Details →BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction
Liwei Ni, Jiaxi Zhang, Shenggen Zheng, Junfeng Liu, Xingyu Meng, Biwei Xie, Xingquan Li*, and Huawei Li. BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pat
Details →AiDRC: Accelerating Detailed Routing by AI-Driven Design Rule Violation Prediction and Checking
Yifan Li, Ruizhi Liu, Zhisheng Zeng, Zengrong Huang, Zhipeng Huang, Dongbo Bu, and Xingquan Li*. AiDRC: Accelerating Detailed Routing by AI-Driven Design Rule Violation P
Details →AiLO: A Predictive Framework for Logic Optimization Using Multi-Scale Cross-Attention Transformer
Ye Cai, Rui Wang, Liwei Ni, Miao Liu, Xingyu Meng, Xiaoze Lin, Junfeng Liu, Biwei Xie, and Xingquan Li*. AiLO: A Predictive Framework for Logic Optimization Using Multi-S
Details →iPO: Constant Liar Parameter Optimization for Placement with Representation and Transfer Learning
Xinhuan Lai, Miao Liu, Xingquan Li*, Yihang Qiu, Shijian Chen, Xinhao Li, Jungang Xu*, iPO: Constant Liar Parameter Optimization for Placement with Representation and Tra
Details →AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing
He Liu, Zhisheng Zeng, Simin Tao, Yifan Li*, Biwei Xie, Wei Gao, Xingquan Li, AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routi
Details →OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis.
Liwei Ni, Rui Wang, Miao Liu, Xingyu Meng, Xiaoze Lin, Junfeng Liu, Guojie Luo, Zhufei Chu, Weikang Qian, Xiaoyan Yang, Biwei Xie, Xingquan Li*, and Huawei Li, " OpenLS-D
Details →iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree.
Weiguo Li, Zhipeng Huang, Bei Yu, Wenxing Zhu, Jian Chen, Zhixue He, Xingquan Li*, " iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree. ",
Details →A Delay-Driven Iterative Technology Mapping Framework.
Junfeng Liu, Liwei Ni, Lei Chen, Xing Li, Qinghua Zhao, Xingquan Li, Shuai Ma*, " A Delay-Driven Iterative Technology Mapping Framework. ", IEEE Transactions on Computer-
Details →QR-DeepONet: Resolve abnormal convergence issue related to basis dimension in DeepONet.
Jie Zhao, Biwei Xie, and Xingquan Li, " QR-DeepONet: Resolve abnormal convergence issue related to basis dimension in DeepONet. ", Machine Learning, Science, 2025. (SCI Q
Details →Delay-Driven Rectilinear Steiner Tree Construction
Hongxi Wu, Xingquan Li, Liang Chen, Bei Yu, and Wenxing Zhu*, " Delay-Driven Rectilinear Steiner Tree Construction ", IEEE Transactions on Computer-Aided Design of Integr
Details →AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL.
Hongxi Wu, Zhipeng Huang, Xingquan Li, Wenxing Zhu*，" AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL. " Integration, the VLS
Details →iPCL-M: Pre-training of Chip Layout for Metrics Evaluation and Optimization
Xinhua Lai, He Liu, Weiguo Li, Yihang Qiu, Miao Liu, Simin Tao, Xingquan Li*, Jungang Xu, iPCL-M: Pre-training of Chip Layout for Metrics Evaluation and Optimization ，in
Details →DiffDEG: Diffusion-Enhanced Design Evolution Graph Representation Learning for Post-Layout Optimization
Jiajie Xu, Leilei Jin, Ziyue Han, Yanlong Mao, Liangji Wu, Chenpu Shi, Yunfan Zuo, Lizheng Ren, Hao Yan*, Xingquan Li and Longxing Shi, DiffDEG: Diffusion-Enhanced Design
Details →iPCL: Pre-training for Chip Layout
Xingquan Li*, Weiguo Li, Xinhua Lai, Junfeng Liu, Rui Wang, iPCL: Pre-training for Chip Layout , in Proceedings of the 29th Asia and South Pacific Design Automation Confe
Details →AiEDA-2.0: An Open-source AI-Aided Design (AAD) Library for Design-to-Vector
Yihang Qiu, Zengrong Huang, Weiguo Li, Xinhua Lai, Rui Wang, He Liu, Ping Zhou, Simin Tao, Junfeng Liu, Yifang Li, Xingquan Li*, AiEDA-2.0: An Open-source AI-Aided Design
Details →A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph Extraction
Shijian Chen, Yihang Qiu, Biwei Xie, Mingyu Chen and Xingquan Li*, A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph Extraction ，in Proceedi
Details →Differentiable Net-Moving and Local Congestion Mitigation for Routability-Driven Global Placement
Wenchao Li, Hongxi Wu, Duanxiang Liu, Xingquan Li and Wenxing Zhu*, Differentiable Net-Moving and Local Congestion Mitigation for Routability-Driven Global Placement ，in
Details →An Efficient Parallel Fault Simulator for Functional Patterns on Multi-core Systems
Xiaoze Lin, Liyang Lai*, Huawei Li, Biwei Xie and Xingquan Li, An Efficient Parallel Fault Simulator for Functional Patterns on Multi-core Systems , IEEE/ACM Design, Auto
Details →Toward Advancing 3D-ICs Physical Design: Challenges and Opportunities
Xueyan Zhao, Weiguo Li, Zhisheng Zeng, Zhipeng Huang, Biwei Xie, Xingquan Li*, Yungang Bao, Toward Advancing 3D-ICs Physical Design: Challenges and Opportunities , in Pro
Details →Simultaneous Conjugate Gradient and iAFF-UNet for Accurate IR Drop Calculation
He Liu, Yipei Xu, Simin Tao, Zhipeng Huang, Biwei Xie, Xingquan Li* and Wei Gao, Simultaneous Conjugate Gradient and iAFF-UNet for Accurate IR Drop Calculation , in Proce
Details →NeuralSteiner: Learning Steiner Tree for Overflow-avoiding Global Routing in Chip Design
Ruizhi Liu, ZhishengZeng, Shizhe Ding, Jingyan Sui, Xingquan Li, Dongbo Bu*, NeuralSteiner: Learning Steiner Tree for Overflow-avoiding Global Routing in Chip Design , in
Details →Net Resource Allocation: A Desirable Initial Routing Step
Zhisheng Zeng; Jikang Liu; Zhipeng Huang; Ye Cai; Biwei Xie; Yungang Bao; Xingquan Li*, Net Resource Allocation: A Desirable Initial Routing Step , in Proceedings of Desi
Details →Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree
Weiguo Li; Zhipeng Huang; Bei Yu; Wenxing Zhu; Xingquan Li*, Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree , in Proceedings of Design A
Details →Parallel AIG Refactoring via Conflict Breaking
Ye Cai, Zonglin Yang, Liwei Ni, Junfeng Liu, Biwei Xie, and Xingquan Li*, Parallel AIG Refactoring via Conflict Breaking , in Proceedings of IEEE International Symposium
Details →Instance-level Timing Learning and Prediction at Placement using Res-UNet Network
He Liu, Simin Tao, Zhipeng Huang, Biwei Xie, Xingquan Li* and Ge Li, Instance-level Timing Learning and Prediction at Placement using Res-UNet Network , in Proceedings of
Details →PCT-Cap: Point Cloud Transformer for Accurate 3D Capacitance Extraction
Ye Cai, Yuyao Liang, Zhipeng Luo, Biwei Xie, Xingquan Li*, PCT-Cap: Point Cloud Transformer for Accurate 3D Capacitance Extraction , in proceedings of IEEE International
Details →Enhancing ASIC Technology Mapping via Parallel Supergate Computing
Ye Cai, Zonglin Yang, Liwei Ni*, Biwei Xie, Xingquan Li, Enhancing ASIC Technology Mapping via Parallel Supergate Computing , in proceedings of IEEE International Symposi
Details →AiEDA: An Open-source AI-native EDA Library
Zhipeng Huang, Zengrong Huang, Simin Tao, Shijian Chen, Zhisheng Zeng, Liwei Ni, Chunan Zhuang, Weiguo Li, Xueyan Zhao, He Liu, Biwei Xie, and Xingquan Li*, AiEDA: An Ope
Details →iPD: An Open-source intelligent Physical Design Tool Chain (invited)
Xingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang, Hongxi Wu, Weiguo Li, Zengrong Huang, Liwei Ni, Xueyan Zhao, He Liu, Shuaiying Long, Ruizhi Liu, Xiaoz
Details →iEDA: An Open-source infrastructure of EDA (invited)
Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing
Details →V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting
Ping Zhang, Pengju Yao, Xingquan Li, Bei Yu, and Wenxing Zhu*, “ V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting ” in Proceedings of
Details →Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning
Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie and Xingquan Li*， “ Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning ”, In Proceed
Details →AiMap: Learning to Improve TechnologyMapping for ASICs via Delay Prediction
Junfeng Liu, Liwei Ni, Xingquan Li, Min Zhou, Lei Chen, Xing Li, Qinghua Zhao and Shuai Ma*, “ AiMap: Learning to Improve TechnologyMapping for ASICs via Delay Prediction
Details →iPL-3D: A Novel BilevelProgramming Model for Die-to-Die Placement
Xueyan Zhao, Shijian Chen, Yihang Qiu, Jiangkao Li, Zhipeng Huang*, BiweiXie, Xingquan Liand Yungang Bao, iPL-3D: A Novel BilevelProgramming Model for Die-to-Die Placemen
Details →Handling Orientation and Aspect Ratio of Modules inElectrostatics-based Large Scale Fixed-Outline Floorplanning
Fuxing Huang, Duanxiang Liu, Xingquan Li, Bei Yu and Wenxing Zhu*, Handling Orientation and Aspect Ratio of Modules inElectrostatics-based Large Scale Fixed-Outline Floor
Details →Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions
Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, and Guojie Luo. " Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions ." In Proceedin
Details →iEDA:An Open-Source Intelligent Physical Implementation Toolkit andLibrary
Xingquan Li, Simin Tao, Zengrong Huang, Shijian Chen, Zhisheng Zeng, Liwei Ni, ZhipengHuang, Chunan Zhuang, Hongxi Wu, Weiguo Li, Xueyan Zhao, He Liu, ShuaiyingLong, Wei
Details →Accurate Timing Path Delay Learning using Feature Enhancer withEffective Capacitance
He Liu, Shengkun Wu,Simin Tao, Biwei Xie, Xingquan Li*,and Ge Li. “ Accurate Timing Path Delay Learning using Feature Enhancer withEffective Capacitance ”, In Proceedings
Details →MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA
Liwei Ni, Zonglin Yang,Jiaxi Zhang, Changhong Feng, Jianhua Liu, Guojie Luo, Huawei Li, Biwei Xie and Xingquan Li*. “ MEC: An Open-source Fine-grained Mapping Equivalence
Details →Weight Uncertainty in Transformer Network for the Traveling Salesman Problem
Jie Zhao, Biwei Xie and Xingquan Li*. “ Weight Uncertainty in Transformer Network for the Traveling Salesman Problem ”, In Proceedings of IEEE International Symposium of
Details →An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance Extraction
Shengkun Wu, Biwei Xie, Xingquan Li*， An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance Extraction ，In Proceedings of the 28th Asia and S
Details →Exploiting Architecture Advances ForSparse Solvers In Circuit Simulation
Zhiyuan Yan, Biwei Xie, Xingquan Li, Yugang Bao*, Exploiting Architecture Advances ForSparse Solvers In Circuit Simulation , In Proceedings of the IEEE/ACM Design, Automa
Details →Jiaxi Zhang, Liwei Ni, Shenggen Zheng*, Hao Liu, Xiangfu Zou, Feng Wang, and Guojie Luo. "Enhanced fast Boolean matching
Jiaxi Zhang, Liwei Ni, Shenggen Zheng*, Hao Liu, Xiangfu Zou, Feng Wang, and Guojie Luo. "Enhanced fast Boolean matching based on sensitivity signatures pruning." In Proc
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