iFP · Floorplanning

Core capabilities

iFP is the starting point of the physical design flow: it maps the post-synthesis gate-level netlist onto the chip's physical framework. It defines die size and core region, places IO pads, plans macro placement regions, and sets the foundation for downstream power-network construction and standard-cell placement. At its core, iFP is an explorable floorplanning engine—not a one-shot run, but a tool that lets Agents generate multiple candidate solutions within the constraint space and compare them.

Agents use iFP heavily in these scenarios: aspect ratio search—under a fixed area budget, try aspect ratios from 0.5 to 2.0 and observe estimated impact on routing congestion and timing; macro placement optimization—try different corner/edge positions for hard macros such as SRAM, PLL, and ADC, and analyze effects on standard-cell region continuity and routing resources; IO placement validation—check IO pad alignment with bumps/pad rings, uniform distribution of power pads, and proximity between signal IOs and internal blocks; floorplan constraint validation—verify physical feasibility of die/core area, placement blockages, halos, and other constraints, catching infeasible floorplans early.

In AI-assisted flows, Agents can batch-generate floorplan candidates with iFP, extract geometric features from each candidate (die area, core utilization, macro spread, standard-cell region connectivity) as vectors, feed them to learning models to predict final QoR (timing, congestion, routability), and automatically select the top-k floorplans. This generate→extract→predict→filter workflow can compress floorplan exploration from days of manual iteration to tens of minutes.

iFP floorplan algorithms support sequence-pair and B*-tree representations, combined with simulated annealing or analytical solvers for constraint resolution. Agents can steer floorplan generation by tuning simulated-annealing parameters (initial temperature, cooling rate, iteration count) and adjusting cost-function weights for area, wirelength, timing, and congestion. Results persist in iDB; downstream tools (iPDN, iPL) can reference floorplan_ref directly for placement context.

Agent calling patterns

# Agent calls iFP to generate a floorplan
from ieda_client import IEDAClient

client = IEDAClient()

# Basic floorplan — fixed aspect ratio and utilization
result = client.call("iFP.plan",
    design_ref="snap_7f3a",
    aspect_ratio=1.0,
    utilization=0.7)

# Agent sweeps aspect_ratio to generate candidates
candidates = []
for ar in [0.6, 0.8, 1.0, 1.2, 1.4]:
    fp = client.call("iFP.plan",
        design_ref="snap_7f3a",
        aspect_ratio=ar,
        utilization=0.7)
    candidates.append(fp)

# Agent evaluates candidates by die_area and core_area
best = min(candidates, key=lambda c: c['die_area'])
print(f"Best floorplan: {best['floorplan_ref']}")

{
  "tool": "iFP.plan",
  "arguments": {
    "design_ref": "snap_7f3a",
    "aspect_ratio": 1.0,
    "utilization": 0.7
  }
}

# Tcl interactive floorplanning
iFP::set_design snap_7f3a
iFP::set_aspect_ratio 1.0
iFP::set_utilization 0.7
iFP::create_floorplan
iFP::place_io -side {top bottom left right}
iFP::place_macro -macro_list {sram_0 sram_1 pll}
iFP::report_area
iFP::export_def -output snap_7f3a.floorplan.def

Input / output contract

Role in the flow

  iMap / iNO synthesis output (netlist)
        │
        ▼
  ┌─────────────┐
  │   iFP      │  ← Current tool: Floorplanning
  │  Floorplan   │
  └──────┬──────┘
         │  floorplan_ref
         ▼
  ┌─────────────┐
  │   iPDN      │  Power grid construction
  │  Power Grid  │
  └──────┬──────┘
         │
         ▼
  ┌─────────────┐
  │    iPL      │  Standard-cell placement (global/legalize/detailed)
  │  Placement   │
  └──────┬──────┘
         │
    ··· Later steps ···

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