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PLATFORM · L1 UNIFIED BASE

Unified base for
Agent-native EDA

iDB + Platform + Interface + Evaluation + Performance—so every Agent call has deterministic state, artifacts, and feedback.

iDB Details → Interface → Evaluation →
iEDA Platform
# Agent loads design, takes snapshot, calls tools
$ agent.load("aes_core", tech="sky130")
→ DesignState { cells: 125430, nets: 98420, ... }
$ agent.call("iDB.snapshot")
→ SnapshotRef { id: "snap_7f3a", time: "2026-07-29T..." }
iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model
MODULES

Five modules

From data to execution, ingress to quality, observation to feedback—each layer gives Agents deterministic boundaries.

CORE · CURRENT · C++20

iDB · Unified design database

Single source of truth for design state with snapshot, typed delta, DirtySet, compare-and-swap commit. All tools share in-memory data; Agents read/write safely via DesignStatePort.

iDB details CORE · D0/DRAFT

Platform · Execution plane

DAG workflow compilation, worker scheduling, resource management, artifact tracking, process recovery. Compiles Agent WorkflowSpec into executable ResolvedWorkflow.

About Platform GATEWAY · D0/DRAFT

Interface · Multi-protocol gateway

Unified MCP/Python/Tcl entry. Typed request/result, secure isolation, lease fencing. Agents need not know the underlying protocol.

Interface details GATE · P0

Evaluation · Quality gate

Metric definitions, Pareto comparison, gate judgment, regret. Every Agent change must pass the gate to commit—otherwise rollback.

Evaluation details OBSERVABILITY · P0

Performance · Observability

Agent call latency, incremental compute cost, closed-loop performance trace. Platform teams see bottlenecks; Agent developers see tool call ROI.

Performance details
DATA FLOW

One dataset, shared globally

One dataset, shared globally

Parsers load Verilog/DEF/LEF/SDC/SPEF/Liberty into iDB; all point tools read/write memory directly—no file handoff or format loss. Agents access the same DesignState via Interface.

DATA FLOW 
Verilog / DEF / LEF / SDC / SPEF / Liberty
           │
           ▼
    ┌──────────────┐
    │     iDB      │ ← Unified design database (single source of truth)
    │  DesignState │
    └──────┬───────┘
           │
    ┌──────┼──────┐
    ▼      ▼      ▼
 ┌────┐ ┌────┐ ┌────┐
 │iPL │ │iRT │ │iSTA│  …  point tools (direct in-memory read/write)
 └────┘ └────┘ └────┘
           │
           ▼
    ┌──────────────┐
    │  Interface   │ ← Agent secure read/write (MCP / Python / Tcl)
    └──────┬───────┘
           ▼
       LLM Agent

Explore the EDA tool chain

Full RTL-to-GDS point tool matrix on the unified base: iMap, iPL, iRT, iSTA, and more.

View EDA tool layer →