iRT · routing engine

# Core capabilities

# Global routing

iRT's global routing stage partitions the routing region into a 3D grid (x, y, layer) and uses maze routing (A* search) to find coarse paths with minimal congestion and controlled wirelength for each net. With effort="estimate", Agents get a fast congestion assessment from global routing only; with effort="standard", the full global routing + track assignment + detail routing flow runs. Global routing output includes per-net demand on each grid edge—exportable to AiEDA Library as congestion feature vectors.

# Track assignment

Track assignment maps coarse global-routing paths onto manufacturing tracks while respecting per-layer preferred direction, minimum spacing, and other process rules. It optimizes wire positions while preserving global routing topology, providing a high-quality starting point for detail routing. Agents can lock already optimized nets via frozen_nets and run track assignment only on new or modified nets.

# Detail routing

Detail routing starts from track assignment results and routes each net segment-by-segment on the manufacturing grid. It supports multi-width metal wires, via arrays, and non-default rule (NDR) width/spacing. The core Agent capability: via the nets parameter, iRT rip-up and reroutes only those nets and their immediate neighborhoods; completed routes locked by frozen_nets remain untouched. Agents can iteratively fix local DRC—one or a few nets at a time—without rerouting the entire chip from scratch.

# Partial rip-up and reroute

Combining nets and frozen_nets, Agents get precise local re-route: specify nets to fix, lock all others, and iRT runs maze search within the new constraint boundary. After completion, drc_count reports remaining DRC violations and failed_nets lists nets that could not be routed. Agents use this to decide next steps—try different net ordering, adjust routing parameters, or escalate for human review.

# Agent calling patterns

iRT exposes three equivalent calling protocols.

from ieda import Client

client = Client("http://localhost:9099")

# Standard full-flow routing
result = client.call(
    "iRT.route",
    design_ref="snap_7f3a",
    effort="standard",
)

print(result.completed_nets)  # 12802
print(result.failed_nets)     # 0
print(result.drc_count)       # 0
print(result.wirelength)      # 4.2e6
print(result.via_count)        # 24531

# Partial re-route: only fix specific nets
partial = client.call(
    "iRT.route",
    design_ref="snap_7f3a",
    effort="in-design",
    nets=["net_1234", "net_5678"],
    frozen_nets=["net_0001", "net_0002", "..."],
)
print(partial.drc_count)    # 3  (remaining violations)
print(partial.failed_nets)  # ["net_5678"]

# Quick congestion estimation
est = client.call(
    "iRT.route",
    design_ref="snap_7f3a",
    effort="estimate",
)

// JSON-RPC over MCP
{
  "jsonrpc": "2.0",
  "method": "tools/call",
  "params": {
    "name": "iRT.route",
    "arguments": {
      "design_ref": "snap_7f3a",
      "effort": "standard",
      "nets": ["net_1234", "net_5678"],
      "frozen_nets": ["net_0001"]
    }
  }
}

// Response
{
  "completed_nets": 12802,
  "failed_nets": 0,
  "drc_count": 0,
  "wirelength": 4200000.0,
  "design_ref": "snap_7f3a_v3",
  "via_count": 24531
}

# Full routing flow
iRT::route -design snap_7f3a -effort standard

# Individual stage control
iRT::run_gr -design snap_7f3a
iRT::run_ta -design snap_7f3a
iRT::run_dr -design snap_7f3a

# Partial re-route
iRT::route -design snap_7f3a -effort in-design \
    -nets {net_1234 net_5678} \
    -frozen_nets {net_0001 net_0002}

# Query results
iRT::report_wirelength
iRT::report_drc
iRT::report_via_count

# Input / output contract

Request Schema — iRT.route

Result Schema

# Role in the flow

RTL
 ↓
 iMap (Synth)
 ↓
 iFP (floorplanning)
 ↓
 iPDN (power grid)
 ↓
 iPL (Place)
 ↓
 iCTS (Clock tree synthesis)
 ↓
 iTO (timing optimization)
 ↓
────────────────────────────
 ↓
◆ iRT (routing engine)      ← upstream: post-placement DEF + clock tree + timing-optimized netlist
 │                         → input: LEF/DEF, design rules, RC tech files
 │  [global routing]              ↔ iSTA (pre-route timing estimation)
 │  [track assignment]
 │  [detail routing]              ↔ iDRC (live DRC check)
 │                         ↔ iRCX (parasitic extraction for iSTA signoff)
 ↓
────────────────────────────
 ↓
 iDRC (Design rule check)
 ↓
 iLVS (layout vs. schematic)
 ↓
 GDSII

# Related resources