iSTA · Static timing analysis

# Core capabilities

# Multi-model delay calculation

iSTA supports three industry-standard delay models: NLDM (Non-Linear Delay Model) for fast estimation, Elmore for first-moment delay on RC trees, and CCS (Composite Current Source) for signoff-level accuracy. Agents pick models by flow stage—NLDM for early placement exploration, CCS for signoff verification. All intermediate results (cell delay, net delay, slew) export as structured vectors via AiEDA Library.

# Incremental timing analysis (dirty cone)

This is iSTA's most valuable capability for Agent workflows. When upstream tools (e.g. iPL) move cells or iTO optimizes local paths, Agents need not rerun full-chip STA. With dirty_only=true, iSTA tracks dirty cells and nets in their fan-in/fan-out cones only, updating delay and slack in that region. Incremental runs typically take 5–15% of full-chip time, giving second-scale timing feedback.

# Typed Timing Report

iSTA produces structured, typed timing reports—not text dumps. Agents set the number of critical paths via the paths parameter; results group by endpoint with per-stage detail (cell, delay, slew, slack). Reports include coverage (share of endpoints analyzed) and provenance (corner, parasitics files, constraints)—so Agents understand timing state without parsing logs.

# Multi-scenario parallel analysis

A single iSTA.analyze call can analyze multiple PVT scenarios (Process, Voltage, Temperature), e.g. ["func_typical", "func_worst", "func_best"]. Results return grouped by scenario so Agents can compare WNS/TNS and worst paths across corners. Multi-scenario analysis runs in parallel threads inside the engine.

# Agent calling patterns

iSTA exposes three equivalent calling protocols.

from ieda import Client

client = Client("http://localhost:9099")

# Full timing analysis across multiple scenarios
timing = client.call(
    "iSTA.analyze",
    design_ref="snap_7f3a",
    scenarios=["func_typical", "func_worst"],
    paths=100,
)

# Structured access
print(timing.wns)              # -0.032  (ns, negative = violation)
print(timing.tns)              # -0.45   (total negative slack)
for p in timing.critical_paths[:3]:
    print(p.slack, p.startpoint, p.endpoint)
print(timing.endpoint_slacks.keys())

# Incremental: only re-analyze dirty cones
incr = client.call(
    "iSTA.analyze",
    design_ref="snap_7f3a_v2",
    scenarios=["func_worst"],
    dirty_only=True,
    endpoints=timing.dirty_set,  # from upstream tool
)
print(incr.coverage)  # CoverageReport: what was analyzed

// JSON-RPC over MCP
{
  "jsonrpc": "2.0",
  "method": "tools/call",
  "params": {
    "name": "iSTA.analyze",
    "arguments": {
      "design_ref": "snap_7f3a",
      "scenarios": ["func_worst"],
      "paths": 50,
      "dirty_only": false
    }
  }
}

// Response
{
  "wns": -0.032,
  "tns": -0.45,
  "critical_paths": [
    {"slack": -0.032, "startpoint": "u_core/reg_0/Q",
     "endpoint": "u_core/reg_1/D", "stages": ["..."]}
  ],
  "endpoint_slacks": {"u_core/reg_1/D": -0.032, "...": 0.12},
  "coverage": {"endpoints_analyzed": 9842, "endpoints_total": 10000},
  "provenance": {"scenario": "func_worst", "parasitics": "snap_7f3a.spef"}
}

# Full timing analysis
iSTA::analyze -design snap_7f3a -scenarios {func_worst} -paths 100

# Incremental analysis on dirty cone only
iSTA::analyze -design snap_7f3a_v2 -scenarios {func_worst} -dirty_only true

# Focus on specific endpoints
iSTA::analyze -design snap_7f3a -endpoints {u_core/reg_1/D u_core/reg_2/D}

# Query results
iSTA::report_wns
iSTA::report_tns
iSTA::report_critical_paths -count 10
iSTA::report_endpoint_slack -pin u_core/reg_1/D

# Input / output contract

Request Schema — iSTA.analyze

Result Schema

# Role in the flow

iSTA is flow-wide infrastructure—not only at timing signoff.

  RTL
   ↓
 iMap (Synth)      ←→ iSTA (post-synth timing check)
   ↓
 iFP (Floorplan)         ←→ iSTA (early timing estimate)
   ↓
 iPDN (Power grid)  ←→ iSTA (IR-drop-aware timing)
   ↓
 iPL (Place)       ←→ iSTA (post-place annotation → incremental)
   ↓
 iCTS (Clock tree) ←→ iSTA (clock delay + skew)
   ↓
 iTO (Timing opt)  ←→ iSTA (incremental verify after each opt step)
   ↓
 iRT (Route)       ←→ iSTA (post-route signoff with parasitics)
   ↓
 iECO (ECO)        ←→ iSTA (local incremental verify)
   ↓
 Signoff         ←→ iSTA (multi-corner full-chip signoff)

# Related resources