Core capabilities
iNO (Netlist Optimization) is the critical bridge between logic synthesis and physical implementation. Gate-level netlists from synthesis tools (iMap) are logically correct but often need fixes before place and route: high-fanout nets (one net driving hundreds of sinks), missing buffer stages, logic redundancy, and structures ill-suited for backend placement and routing. iNO performs this netlist cleanup and physical preparation between iMap output and iFP floorplanning.
Agents use iNO as the core tool for netlist quality diagnosis and automatic repair. Typical scenarios include: high-fanout diagnosis—Agents call iNO to scan the netlist, find all nets exceeding the max_fanout threshold, and generate per-net fanout reports; for violators, iNO proposes N-ary buffer trees for Agent review and application; physical readiness checks—before floorplanning, Agents run iNO in full mode (fanout+buffer+full) to ensure drive strength, fanout, and logic depth meet backend requirements; area–timing trade-off analysis—Agents try different max_fanout values (16/32/64), compare buffer count and area growth, and pick the optimal trade-off.
In AI-assisted flows, Agents can collect iNO repair history (which net types tend toward high fanout, which buffer strategies work best per process) and train models to predict buffer resources at synthesis time—reserving buffer placement regions during floorplanning to avoid congestion when buffers have nowhere to go.
iNO supports three optimization modes: fanout mode fixes fanout violations only (minimal change); buffer mode repairs fanout and optimizes buffer chains (signal integrity); full mode runs complete netlist restructuring (logic redundancy removal, inverter-pair merging, constant propagation, and other general optimizations). Agents pick the mode by flow stage—full cleanup right after synthesis, fanout-only for minimal ECO changes.
Agent calling patterns
# Agent calls iNO for netlist optimization
from ieda_client import IEDAClient
client = IEDAClient()
# Basic optimization — repair high fanout
result = client.call("iNO.optimize",
design_ref="snap_7f3a",
max_fanout=32)
print(f"Fanout violations fixed: {result['fanout_violations_fixed']}")
print(f"Buffers inserted: {result['buffers_inserted']}")
print(f"Area change: {result['area_change']:+.2f}%")
# Agent can diagnose first, then choose optimize parameters
diag = client.call("iNO.diagnose",
design_ref="snap_7f3a")
high_fanout_nets = [n for n in diag if n['fanout'] > 64]
print(f"Critical high-fanout nets: {len(high_fanout_nets)}")
# Full-mode optimization — thorough netlist cleanup
result = client.call("iNO.optimize",
design_ref="snap_7f3a",
max_fanout=32,
optimization_mode="full")
{
"tool": "iNO.optimize",
"arguments": {
"design_ref": "snap_7f3a",
"max_fanout": 32,
"optimization_mode": "full"
}
}
# Tcl interactive netlist optimization
iNO::set_design snap_7f3a
iNO::set_max_fanout 32
iNO::set_optimization_mode full
iNO::diagnose -report high_fanout.txt
iNO::optimize
iNO::report_changes
iNO::write_netlist -output snap_7f3a.opt.v
Input / output contract
| Field | Type | Required | Description |
|---|---|---|---|
design_ref | string | Yes | Design instance ID (includes post-synthesis netlist) |
max_fanout | int | Yes | Maximum allowed fanout (buffer trees inserted when exceeded) |
buffer_types | string[] | No | Available buffer/inverter cell types |
optimization_mode | "fanout"|"buffer"|"full" | No | Optimization mode (default: fanout) |
| Return field | Type | Description |
|---|---|---|
optimized_netlist_ref | string | Optimized netlist reference ID in iDB |
fanout_violations_fixed | int | Number of fanout violations repaired |
buffers_inserted | int | Total buffers/inverters inserted |
area_change | float | Area change percentage (positive = increase) |
Role in the flow
RTL Source
│
▼
┌─────────────┐
│ iMap │ Logic synthesis (RTL → gate netlist)
│ Synthesis │
└──────┬──────┘
│ raw netlist (may have high fanout)
▼
┌─────────────┐
│ iNO │ ← Current tool: Netlist optimization
│ Netlist Opt │
└──────┬──────┘
│ cleaned netlist
▼
┌─────────────┐
│ iFP │ Floorplanning (first physical step)
│ Floorplan │
└──────┬──────┘
│
... Later steps ...
Related resources
Paper
Bartlett KA, et al. "Synthesis and Optimization of Multilevel Logic under Timing Constraints." IEEE TCAD, 1986.
View →Paper
Alpert CJ, et al. "Buffer Insertion for Noise and Delay Optimization." IEEE TCAD, 1999.
View →Related tool
iMap · Logic synthesis — upstream; synthesis quality determines how much iNO must repair.
iMap →Related tool
iFP · Floorplanning — iNO's clean netlist is the required input for floorplanning.
iFP →Team
iNO is maintained by the iEDA community; contributions welcome for buffer insertion and logic restructuring algorithms.
Contact →