The standard cell library is an integral part of the modern ASIC design flow, providing designers with a set of predefined logic cells that can significantly reduce design time and improve design reliability and performance. In physical design, the standard cell library plays a crucial role. It contains a variety of cell types, including cells with different drive strengths and threshold voltages, as well as some specialized physical cells. In this article, I will introduce in detail the important contents of standard cell libraries and their application in ASIC design.
Pre-characterization:
First, let's look at the pre-characterization process of the standard cell library. Before cells are included in the standard cell library, they undergo a rigorous design process. This process includes schematic design, simulation verification, symbol creation, layout design (following standard cell layout rules), physical verification, abstraction, extraction, and characterization. Through these steps, designers can ensure that standard cells are reliable in terms of functionality and performance and comply with various physical design rules so that they can be used smoothly during the subsequent automated place and route (APR) process.
Multi-drive strength unit:
An important concept in the standard cell library is the multi-drive strength cell. Different units have different driving strengths, which directly affects the power consumption, area and timing performance of the design. Low drive strength units typically have lower power and area requirements but result in higher latency and transition times. In contrast, high-driving intensity cells can drive more cells and have faster switching speeds, but consume more power and area. Therefore, PnR design engineers need to choose the appropriate drive strength according to specific requirements during the design process to balance the power consumption, area and performance of the design.
Multi-threshold voltage [Vt] unit:
The standard cell library also includes multi-threshold voltage (Vt) cells. Vt units are designed for different power consumption and timing requirements. Low threshold voltage (LVT) cells have shorter latency but incur higher leakage power. Their counterparts are high-threshold voltage (HVT) cells, which have lower leakage power but incur higher latency. Based on the timing and power consumption requirements of the design, PnR engineers can select appropriate Vt cells in the standard cell library to achieve a balance between power consumption and timing. Modern standard cell libraries usually contain ULVT, LVT, SVT, HVT and other types of cells, arranged in order of increasing threshold voltage.
Physical unit:
In addition to logical cells, the standard cell library also includes some cells specifically for physical design. These physical units have no logical function but are used to mitigate various impacts and manufacturing issues. For example, to overcome the latch-up phenomenon of the latch, we need to add well contact cells. In addition, there are special units such as Decap unit, endcap unit, antenna unit and filling unit, which play a key role in the physical design process.
Unit collection:
Through the standard cell library, designers can greatly simplify and speed up the ASIC design process by selecting and using predefined, verified and characterized standard cells. The standard unit library covers a variety of logical and physical units, including basic gates (such as AND, OR, NOT, etc.), complex gates (such as MUX, HA, FA, comparators, etc.), clock tree units (such as clock buffers, clock inverters, ICG units, etc.), flip-flops, latches, delay units, physical units, and scannable flip-flops. Generally speaking, the standard cell library contains the following types of cells:
- All basic and general gates (such as AND, OR, NOT, NAND, NOR, XOR, etc.)
- Complex gates (such as MUX, HA, FA, comparator, AOI, OAI, etc.)
- Clock tree units (such as clock buffers, clock inverters, ICG units, etc.)
- Flip-flops and latches
- delay unit
- physical unit
- scannable trigger
File collection:
In addition, the standard cell library covers a collection of files related to automatic placement and routing. These files include LIB files, LEF files, netlist files, GDS files, SPICE netlists and model files. The LIB file is a timing library that contains the delay, power consumption and area information of the unit for subsequent timing analysis and optimization. The LEF file is a physical library file that provides an abstract view of the cell layout, including the cell's boundaries, pins, location, orientation, and metal layer information. The netlist file is a Verilog file of a standard unit and is used to describe the function of the unit. GDS files are physical layout files of standard cells and are used for actual chip manufacturing. SPICE netlist is a format used for circuit simulation to verify the functionality and characteristics of a design. The model file contains various design parameters of the unit and can be used for SPICE simulation. These documents mainly include:
- LIB file (.lib)
- LEF file (.lef)
- Netlist file (.v)
- GDS files (.gds)
- SPICE netlist (.sp)
- Model file (.m)
All file formats mentioned here refer to Cadence tools. In Synopsys tools, some file formats are different, but the information within the files is the same. Brief information about these files is given in the "VLSI Files" section of this blog. Details can be found in this section.
Timing library (LIB or DB) files are generated during unit characterization. Library files contain cell delay, power, and area information. A physical library (LEF) file is an abstract view of the cell layout. The LEF file contains cell boundaries, pins within the cell, location, orientation, and metal layer information for each pin. The netlist file is a Verilog file of a standard unit that defines the function of the unit. A GDS file is a layout of standard cells. A SPICE netlist is a netlist of cells in SPICE format, used for simulation. The model file contains various design parameters required by the unit for SPICE simulation.
In general, standard cell libraries play a vital role in modern ASIC design. It provides a rich variety of predefined logic units, allowing designers to complete designs quickly and efficiently. By selecting appropriate drive strength and threshold voltage cells, designers can find the best balance between area, power consumption, and performance. In addition, the physical units and corresponding file collection ensure the reliability and manufacturability of the design.
I hope that through the introduction of this article, readers will have a deeper understanding of the importance and application of standard cell libraries. In actual ASIC design, reasonable selection and use of standard cell libraries will be one of the keys to success.
References
Original link:https://teamvlsi.com/2020/08/standard-cell-library-in-asic-design.html