CATALOG
Chip design stages
Chip design link — learning path connecting EDA fundamentals to open practice.
In this section
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3.1 Logic synthesis stage
Logic synthesis inherits the circuit design (.v file) at the RTL level, and the physical …
023.2 Layout planning and power supply planning
The logic synthesis phase outputs the gate-level netlist and design constraint file (SDC)…
033.3 Layout stage
The placement of I/O units and modules in the layout category is completed during layout …
043.5 Clock tree synthesis
Clock tree synthesis is performed immediately after layout. Clock tree synthesis problem:…
053.5 Wiring stage
Placement and clock tree synthesis are followed by routing operations. Main topics: To co…