Skip to main content

ACTIVITIES

Contest
open documentation

2024 Integrated Circuit EDA Elite Challenge - Topic:

Enter section → Home

4 pagesOpen docsAI-readyBilingual

ieda — contests

# open iEDA stack
$ ieda open contests
[nav ] module linked         ok
[docs] pages indexed         ok
[ai  ] state exportable      ok
→ continue exploring

iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model

4Pages here

RTL→GDSOpen flow

AIExportable state

GPL-3.0License

Section map

Pick a path into this module

Each card opens a maintained page in the open documentation set.

2023 Integrated Circuit EDA Elite Challenge - Topic 2

Open this section of the open stack.

Learn more PAGE

2023 openDACS Open EDA and Chip Design Competition-Topic 1

Open this section of the open stack.

Learn more PAGE

2023 openDACS Open EDA and Chip Design Competition-Topic 2

Open this section of the open stack.

Learn more PAGE

2023 openDACS Open EDA and Chip Design Competition-Topic 3

Open this section of the open stack.

RTL → GDSII

One database across the entire flow

01

iMap

Logic synthesis

02

iFP

Floorplanning

03

iPDN

Power delivery

04

iPL

Placement

05

iCTS

Clock tree

06

iTO

Optimization

07

iRT

Routing

08

iDRC

Rule checks

INDEX

Learning tracks

Grouped by track — open a week card to continue.

Overview pages

4 pages

2023 Integrated Circuit EDA Elite Challenge - Topic 2EDA_elite_challenge-23-t2.html

2023 openDACS Open EDA and Chip Design Competition-Topic 1openDACS-23-contest-t1.html

2023 openDACS Open EDA and Chip Design Competition-Topic 2openDACS-23-contest-t2.html

2023 openDACS Open EDA and Chip Design Competition-Topic 3openDACS-23-contest-t3.html

Keep exploring the open stack

Jump to tools, learning, or AiEDA from here.

Toolchain → Contact