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AiMap

Learning model for technology mapping and logic synthesis decisions consuming iEDA open intermediate state.

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doc — aimap
# open iEDA stack
$ ieda open aimap
[nav ] module linked         ok
[docs] pages indexed         ok
[ai  ] state exportable      ok
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iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model
5Pages here
RTL→GDSOpen flow
AIExportable state
GPL-3.0License

AiMap

Problem

Technology mapping has a huge operator search space. AiMap learns from open iEDA states to predict delay / quality and guide mapping decisions alongside iMap.

In the product

  • Upstream: synthesis/netlist features
  • Model: prediction for mapping choices
  • Downstream: better starts for physical design
NAV

Nearby pages

PAGE

AiCap

Open this section of the open stack.

Learn morePAGE

AiMP

Open this section of the open stack.

Learn morePAGE

AiST

Open this section of the open stack.

Learn morePAGE

AiSTA

Open this section of the open stack.

Learn morePAGE

AiTO

Open this section of the open stack.

Learn more

Build with open intermediate state

Every page connects back to executable tools and AI-ready design data.

AiEDA → Contact