Softwares

# Software Links

# Related to iEDA

• iEDA (https://gitee.com/oscc-project/iEDAopen in new window): A 28nm process RTL-GDS II digital chip design platform, creating a high-quality open-source EDA infrastructure and tool platform, supporting EDA academic research, talent cultivation, and key technology incubation. Includes: iLS, iMAP, iNO, iFP, iPDN, iPL, iCTS, iTO, iRT, iDR, iSTA, iPA, iDRC and other tools, as well as basic bases such as analysis, database, evaluation, interface, operation, solver, utility.

• iFlow (https://gitee.com/oscc-project/iFlowopen in new window): Automated chip back-end design process, supporting 130/110/55/28nm processes, from RTL-GDS II automated back-end design full process.

• iMAP (https://gitee.com/oscc-project/iMAPopen in new window): FPGA process mapping tool, supporting the generation from AIG to Netlist.

• iParsers (https://gitee.com/oscc-project/parseropen in new window): Parsers required for EDA standard formats, including verilog, liberty, sdc, spef, sdf, vcd.

# Related to AiEDA

• AiEDA (https://gitee.com/ieda-iai/ai-platformopen in new window): Intelligent EDA framework and toolkit, supporting framework models for multiple AI+EDA tasks, supporting flexible invocation of iEDA tools or mainstream commercial EDA tools for researching and training AI+EDA models.

• iBM (https://gitee.com/oscc-project/i-bmopen in new window): Construction of EDA label datasets.

• AiDelay (https://gitee.com/oscc-project/delay-predictionopen in new window): Delay model based on wire length fitting.

• AiSTA (https://gitee.com/oscc-project/delay-calibrationopen in new window): Res-Unet timing learning model.

• AiCap (https://gitee.com/oscc-project/pct-capopen in new window): 3D capacitance extraction network model represented by point cloud.

# Software Copyrights