Why it matters
Hongxi Wu, Zhipeng Huang, Xingquan Li, Wenxing Zhu*，" AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL. " Integration, the VLSI Journal, 2024. (CCF-C)
Citation entry
Hongxi Wu, Zhipeng Huang, Xingquan Li, Wenxing Zhu*，"AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL." Integration, the VLSI Journal, 2024. (CCF-C)
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