Core capabilities
- Layout–netlist comparison: Extract devices and connectivity from layout; compare against reference netlist device-by-device and net-by-net.
- Flat digital optimization: Fast LVS for flat designs, suited to large digital SoCs.
- Mismatch localization: Device-level (missing/extra/size-mismatch) and net-level (short/open) mismatch reports.
- Multi-format input: Adapter supports GDS/DEF layout and Verilog/SPICE netlist inputs.
- Agent-ready: Python API for automated compare tasks and structured results.
Agent calling patterns
result = client.call("iLVS.compare",
design_ref="snap_7f3a",
netlist_ref="netlist_v1"
)
# result.passed → bool
# result.mismatches → list[Mismatch]
# result.summary → dict (device_count, net_count, match_rate)Input / output contract
| Direction | Parameter | Type | Description |
|---|---|---|---|
| Input | design_ref | str | Layout snapshot (GDS/DEF loaded in iDB) |
| Input | netlist_ref | str | Reference netlist snapshot (Verilog/SPICE) |
| Input | options | dict (optional) | Tolerance, ignored nets, device mapping rules, etc. |
| Output | passed | bool | Overall LVS pass/fail |
| Output | mismatches | list | Per-mismatch details (device/net level, with coordinates) |
| Output | summary | dict | Summary: device count, net count, match rate |
Role in the flow
01 Synth
iMap
Logic synthesis & tech mapping
02 Physical design
iFP · iPL · iCTS · iRT
Full place & route flow
03 Timing signoff
iSTA · iTO
Static timing analysis & optimization
04 Physical signoff
iDRC · iLVS
Design rule check & LVS
iLVS runs in physical signoff after routing, verifying layout against the reference netlist. Together with iDRC it forms the signoff twin pillars.
Related resources
- iDRC — Design rule check: The other half of physical signoff—layout vs. process rules.
- iFormal — Formal verification: Logic equivalence; complements LVS.
- EDA tools overview: Map of all 22 point tools.
- iEDA Platform: Unified iDB is the foundation for LVS comparison.