In the implementation process of digital integrated circuits, EDA tools and various technical documents play a key role. In the complex process from RTL to GDSII, EDA tools needaccess, processingdata at various stages and generate importantintermediate files. This intermediate file is used to connect processes and data exchange between different tools.
The following table lists some commonly used library files and documents and their role in the process. The remaining chapters of this section will discuss the ones listed in the table.Some library files and documentationGive a brief introduction.
| Format | latest version | Chinese name | function |
|---|---|---|---|
| VHDL | IEEE1076-2002 | hardware description language | System-level, behavioral-level, and structural-level description languages for circuit functions |
| Verilog HDL | IEEE1364-2001 | hardware description language | System-level, behavioral-level, and structural-level description languages for circuit functions |
| VCD | 1364-1995 | Value Change DumpValue Change Dump | Simulated signal transition information for chip dynamic power consumption analysis |
| SDC | 1.7 | Design Constraints (Format) | Timing, area, and power constraint files for logic synthesis and physical implementation |
| GDSH | 6.0 | Image display standard (format) | It describes the layout level, shape, position and other information. It is a text used by circuit designers and foundries to exchange information. It can also be used for parasitic parameter extraction, power consumption analysis, and voltage drop analysis. |
| LEF | 5.6 | Physics library exchange format | Physical library files for automatic place and route |
| Liberty | 3.0 | Timing library (format) | Library files for synthesis and timing analysis |
| DEF | 5.6 | Design exchange format | The circuit netlist file after layout and wiring can be used for chip parasitic parameter extraction, power consumption analysis, and voltage drop analysis. |
| SPF | 1.5（DSPF）, 1.5（RSPF）, IEEE1481（SPEF） | Detailed standard parasitic format, reduced standard parasitic format, standard parasitic exchange format | Chip parasitic parameter file for SI and STA analysis |
| SDF | 3.0 | Standard delay format | Describe the delay and STA analysis of cells and interconnection lines after placement and routing for front-end simulation |
| CPF | 1.0 | Common power consumption format | Low Power Design Constraints Document |
| TCF | 1.0 | rollover count format | Power consumption analysis, power consumption optimization |
| TWF | 2.0 | Timing window format | Analysis of the impact of noise on delay |
Quote
- "Physical Design of Digital Integrated Circuits" P235