We will discuss the required input files during the various stages of PnR [Place and Route] and Signoff [Signoff]. We can divide the input files into two categories, one is required and the other is optional.
1. PnR stage:
1.1 Pre-layout stage
Required input:
- Gate level netlist
- Logical Library
- Physical Library
- SDC file
Optional input:
- Block partition def
- Pin def
- Power plan script
- Welltap placement rule
- Macro placement guidelines
- MMMC Setup file
- Endpoint unit (EndCap), decoupling capacitor unit (Decap cell) list
- Alternate unit module definitions and rules
These input files are used in the pre-layout phase to guide the layout tool in placing individual elements in the design and ensuring that specific constraints and rules are met. The preparation and correct use of these files is important to obtain good layout and timing performance.
Note:
- Logical libraries, physical libraries and SDC files are required at every stage.
- The netlist is modified at each stage and the updated netlist is used in the next stage.
1.2 Layout
Required input:
- Preplace database
Optional input:
- Placement blockage script
- Path groups script
- Placement setting script
- Timing and Congestion Optimization scripts
- Clock tree constraints (in early clock flow)
1.3 Clock tree synthesis
Required input:
- Placement database
- Clock tree constraints
1.4 Cabling
- Clock Tree Comprehensive Database (CTS database)
1.5 Chip completed
- Route database
- Filler cell list
2. Metal filling
- OASIS/GDS files at the chip completion stage
3. RC extraction
- ICT file/Quantus Techfile (qrcTechFile)
- MMMC settings file
- LEF file
- DEF file
- Merged OASIS/GDS files
These input files are used at various stages of PnR and signoff, covering the different steps from layout to metal fill and RC extraction. The preparation and use of these files and scripts is critical to ensuring that the design achieves the expected performance and layout quality.
4. IR analysis
4.1 Technology/library files
- LEF file (.lef)
- LIB file (.lib)
- Technical files (.tech)
- Standard unit GDS file (.gds)
- GDS layer mapping file
- Device model file*
- SPICE netlist for standard cells*
4.2 Design data
- DEF file
- Netlist file
- SPEF file
- STA file* (timing window, slew, instance frequency, clock domain information)
- VCD file*
- PLOC file*
*File is only used for dynamic analysis
4.3 IR analysis types:
- Static IR analysis
- Dynamic IR analysis
- electromagnetic analysis
5. Static timing analysis
Required input:
- Design netlist
- SDC file
- LIB file
- SPEF file
- MMMC view definition file
Optional input:
- Instance-based IR buck file
- SI library file
- Baseline/incremental delay annotation file
6. Physical verification
6.1 Design Rule Check [DRC]
- Merged GDS files
- DRC rules file
6.2 Polarization effect
- Merged GDS files
- DRC rules file
6.3 Layout and Schematic Check [LVS]
- PD netlist
- Merged GDS files
6.4 Logical Equivalence Check [LEC]
- Golden netlist
- PD netlist
- LEC constraint file (if any)
thank you
Original link:https://teamvlsi.com/2021/11/input-files-required-for-pnr-and.html