Clock tree synthesis is the process of building and optimizing a clock tree in such a way that the clocks are evenly distributed and the clocks of each sequential element are within the target global skew limits. To build a clock tree, we have to provide certain constraints as input to the APR tool, these constraints are often called clock constraints, and for Innovus tools, this constraints file is often called a ccopt file.
In this article, we will look at some important clock tree constraints that are commonly used in every design, what they actually mean and why they are provided. Nowadays, if you are going for an interview for physical design and your experience is between 0-5 years, you will inevitably face questions related to clock tree constraints.
Clock tree constraints:
- Clock tree unit list
- Preferred clock tree routing layers and non-default rules (NDR)
- target offset
- target maximum transition
- Target maximum capacitance
- Maximum fan-out
- cell density
- Leave cell borders blank
Clock tree unit list
We use clock inverters and clock buffers in clock tree construction. Sometimes we just use clock inverter instead of clock buffer. We also use clock gating cells in the clock tree. Therefore, we must provide a list of cells that we want to use in the clock tree.
set_ccopt_property inverter_cells {}
set_ccopt_property buffer_cells {}
set_ccopt_property clock_gating_cells {}
set_ccopt_property logic_cells {}
Preferred clock tree routing layers and non-default rules (NDR)
We need top and bottom preferred routing layers for the clock tree network. Usually we define the backbone network and leaf network here. The network that connects the clock to the clock pin of the sequential element is called a leaf net, and the network that delivers the clock to the leaf net is called a backbone.
set_ccopt_property -name trunckRoute -top_preferred_layer <> -bottom_preferred_layer <> -preferred_routing_layer_effort high -non_default_rule 2w2s
set_ccopt_property -name leafRoute -top_preferred_layer <> -bottom_preferred_layer <> -preferred_routing_layer_effort high -non_default_rule 1w2s
target offset
Offset balancing is one of the challenges in clock tree optimization. We provide the target offset as a clock tree constraint. The PnR tool will attempt to balance the offset within the given offset limits.
set_ccopt_property -target_skew <>
target maximum transition
We provide clock tree networks with maximum transition limits for clock nets. The tool will try to satisfy the maximum transition limit.
set_ccopt_property -target_max_trans <>
Target maximum capacitance
We provide a maximum capacitance limit for the clock net for the clock tree network. The tool will try to distribute the load capacitance and try to meet the maximum capacitance limit.
set_ccopt_property -target_max_capacitance <>
Maximum fan-out
We limit the maximum fanout of any instance in the clock tree through this constraint. The tool will try to build the clock tree according to this limit.
set_ccopt_property -max_fanout <>
cell density
Setting a maximum cell density limit on clock tree instances is required.
set_ccopt_property -cell_density <>
Leave cell borders blank [Halo]
We need to provide a Halo around the clock tree instance to avoid IR/crosstalk issues that might result from more dense placement. Therefore, we provide cell boundary margin constraints in the x and y directions around the cell.
set_ccopt_property -cell_halo_x <>
set_ccopt_property -cell_halo_y <>
These are the main constraints provided before building the clock tree. There are some other constraints, but the main ones have been explained in the above sections. The following figure summarizes the clock tree constraints.
**Thank you**
Original link:https://teamvlsi.com/2021/06/clock-tree-constraints-in-vlsi-ccopt-file-in-physical-design-cts-constraints.html