Second Tapeout: 20220812, 1.5M-gate-level processor chip designed in the "One Chip for a Lifetime" 110nm technology, third phase, achieved a 25MHz tapeout result;
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iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model
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Chip Parameters
Second Tapeout: 20220812, 1.5M-gate-level processor chip designed in the “One Chip for a Lifetime” 110nm technology, third phase, achieved a 25MHz tapeout result;
SoC Specifications:
A 11-stage, single-issue RV64I MAC processor core
AXI4 bus interconnect network, with an integrated PLL, designed with three clock domains
