# open iEDA stack$ ieda open chip-data[nav ] module linked ok[docs] pages indexed ok[ai ] state exportable ok→ continue exploring
iMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout modeliMapsynthesisiFPfloorplaniPDNpoweriPLplacementiCTSclockiTOoptimizationiRTroutingiSTAtimingAiEDAdesign dataiPCLlayout model
1Pages here
RTL→GDSOpen flow
AIExportable state
GPL-3.0License
Chip design datasets
Open chip-level snapshots for learning and benchmarking: netlists, layouts, timing/power features, and intermediate iEDA states.
Use with AiEDA Library feature extractors
Pair with tape-out case studies for silicon context