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Logic Engine · ADAPTER-FIRST

iLO-iTM · Logic optimization & tech mapping

Logic optimization and tech mapping external adapter. Agents obtain LogicIR via external synthesis tools; iEDA performs further netlist optimization. CMakeLists.txt is currently empty (D0); adapter-first.

D0/DRAFTWave 4ADAPTER-FIRSTEmpty CMakeLists
agent — ilo-itm
# Logic optimization adapter
$ agent call iLO.optimize
[logic] external synth → LogicIR ok
[opt  ] iEDA-side netlist pass  ok
→ adapter-first · DRAFT
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Core capabilities

  • External synthesis adapter: Call external logic synthesis tools (Yosys/ABC) via adapter and obtain standardized LogicIR.
  • Netlist-level optimization: Further optimize LogicIR on iEDA side—constant propagation, redundancy removal, local restructuring.
  • Tech mapping preparation: Prepare optimized netlists for iMap tech mapping, reducing downstream search space.
  • D0 starting point: CMakeLists.txt is empty; earliest planning stage. Adapter-first—wire external toolchain first, then build in-house.
  • Agent-ready: Python API wraps external synthesis and iEDA-side optimization for one-shot synth-opt-netlist flow.

Agent calling patterns

logic = client.call("iLO.optimize",
    design_ref="snap_7f3a",
    tech="sky130"
)

# logic.optimized_netlist_ref   → str (optimized netlist snapshot)
# logic.logic_ir                → dict (standardized LogicIR)
# logic.optimization_stats      → dict (area/gate count/depth changes)

Input / output contract

DirectionParameterTypeDescription
Inputdesign_refstrDesign snapshot (RTL or unoptimized netlist)
InputtechstrTarget process: sky130 | nangate45 | gf12lp, etc.
Inputsynth_toolstr (optional)External synth tool: yosys | genus | dc, default yosys
Outputoptimized_netlist_refstrOptimized netlist snapshot reference
Outputlogic_irdictStandardized LogicIR: nodes, edges, attributes
Outputoptimization_statsdictOptimization stats: original gates, optimized gates, depth change

Role in the flow

01 RTL

Verilog/VHDL

Register-transfer level description

02 Logic opt

iLO · iTM

Pre-synthesis optimization & tech mapping

03 Tech mapping

iMap

Target library binding

04 Physical design

iFP · iPL · iCTS · iRT

Full place & route flow

iLO-iTM sits after RTL and before tech mapping—the upstream-most tool in the RTL→GDS flow. Works with iMap to complete the HDL-to-gate-netlist conversion chain.

Keep building with open intermediate state

Every page links back to executable tools and AI-ready design data.