Core capabilities
- External synthesis adapter: Call external logic synthesis tools (Yosys/ABC) via adapter and obtain standardized LogicIR.
- Netlist-level optimization: Further optimize LogicIR on iEDA side—constant propagation, redundancy removal, local restructuring.
- Tech mapping preparation: Prepare optimized netlists for iMap tech mapping, reducing downstream search space.
- D0 starting point: CMakeLists.txt is empty; earliest planning stage. Adapter-first—wire external toolchain first, then build in-house.
- Agent-ready: Python API wraps external synthesis and iEDA-side optimization for one-shot synth-opt-netlist flow.
Agent calling patterns
logic = client.call("iLO.optimize",
design_ref="snap_7f3a",
tech="sky130"
)
# logic.optimized_netlist_ref → str (optimized netlist snapshot)
# logic.logic_ir → dict (standardized LogicIR)
# logic.optimization_stats → dict (area/gate count/depth changes)
Input / output contract
| Direction | Parameter | Type | Description |
|---|---|---|---|
| Input | design_ref | str | Design snapshot (RTL or unoptimized netlist) |
| Input | tech | str | Target process: sky130 | nangate45 | gf12lp, etc. |
| Input | synth_tool | str (optional) | External synth tool: yosys | genus | dc, default yosys |
| Output | optimized_netlist_ref | str | Optimized netlist snapshot reference |
| Output | logic_ir | dict | Standardized LogicIR: nodes, edges, attributes |
| Output | optimization_stats | dict | Optimization stats: original gates, optimized gates, depth change |
Role in the flow
01 RTL
Verilog/VHDL
Register-transfer level description
02 Logic opt
iLO · iTM
Pre-synthesis optimization & tech mapping
03 Tech mapping
iMap
Target library binding
04 Physical design
iFP · iPL · iCTS · iRT
Full place & route flow
iLO-iTM sits after RTL and before tech mapping—the upstream-most tool in the RTL→GDS flow. Works with iMap to complete the HDL-to-gate-netlist conversion chain.
Related resources
- iMap — Tech mapping: iLO output feeds directly into iMap for library binding.
- iNO — Netlist optimization: Finer-grained netlist-level optimization.
- EDA tools overview: Map of all 22 point tools.